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Book 1 

Programming 
with the 

PDP-10 
Instruction Set 



PDP-10 
System Reference Manual 



Changes are indicated by a triangle (A) in the outside margin 



Contents 



1 


INTRODUCTION 


1-1 


1.1 


Number System 

Floating point arithmetic 1-5 


1-4 


1.2 


Instruction Format 

Effective address calculation 1-7 


1-6 


1.3 


Memory 

Memory allocation 1-9 


1-8 


1.4 


Programming Conventions 


1-10 


2 


CENTRAL PROCESSOR 


2-1 


2.1 


Half Word Data Transmission 


2-2 


2.2 


Full Word Data Transmission 
Move instructions 2-10 
Pushdown list 2-12 


2-9 


2.3 


Byte Manipulation 


2-15 


2.4 


Logic 

Shift and rotate 2-24 


2-17 


2.5 


Fixed Point Arithmetic 
Arithmetic shifting 2-31 


2-26 


2.6 


Floating Point Arithmetic 
Scaling 2-33 

Operations with rounding 2-34 
Operations' without rounding 2-37 


2-32 


2.7 


Arithmetic Testing 


2-41 


2.8 


Logical Testing and Modification 


2-47 


2.9 


Program Control 


2-54 


2.10 


Unimplemented Operations 


2-64 


2:11 


Programming Examples 

Double precision floating point 2-67 


2-65 


2.12 


Input-Output 

Readin mode 2-72 
Console data transfers 2-73 


2-68 



VI 



2.13 


Priority Interrupt 


2.14 


Processor Conditions 


2.15 


Time Sharing 




User programming 2-82 




Monitor programming 2-83 


2.16 


Operation 




Indicators 2-84 




Operating keys 2-87 




Operating switches 2-89 


3 


BASIC IN-OUT EQUIPMENT 


3.1 


Paper Tape Reader 




Readin mode 3-4 


3.2 


Paper Tape Punch 


3.3 


Teletype 


4 ' 


HARDCOPY EQUIPMENT 


4.1 


Line Printer 


4.2 


Plotter 


4.3 


Card Reader 


4.4 


Card Punch 




APPENDICES 



2-73 
2-78 
2-81 

2-84 



3-1 

3-5 

3-7 

4-1 

4-1 

4-9 

4-14 

4-18 



A Instruction and Device Mnemonics Al 

Numeric listing A3 . 

Alphabetic listing A6 
Device mnemonics AlO 

B In-out Codes Bl 

Teletype code B2 
Card codes B6 

C Miscellany / CI 

D Algorithms Dl 

Fixed point algorithms D2 
Floating point algorithms D7 

INDEX II 



AUGUST 1969 



Introduction 



The PDF- 10 is a general purpose, stored program computer that includes a 
central processor, a memory, and a variety of peripheral equipment such as 
paper tape reader and punch, teletype, card reader, line" printer, DECtape, 
magnetic tape, disk file arid display. The central processor is the control unit 
for the entire system: it governs all peripheral in-out equipment, sequences 
the program, and performs all arithmetic, logical and data handling opera- 
tions. The processor is connected to one or more memory units by a mem- 
ory bus and to the peripheral equipment by an in-out bus. The fastest 
devices, such as the disc file, although controlled by the processor over the 
in-out bus, have direct access to memory over a second memory bus. 

The processor handles words of thirty-six bits, which are stored in a mem- 
ory with a maximum capacity of 262,144 words. Storage in memory is 
usually in the form of 37-bit words, the extra bit producing odd parity for 
the word. The bits of a word are numbered 0-35, left to right, as are the 
bits in the registers that handle the words. The processor can also handle 
half words, wherein the left half comprises bits 0-17, the right half, bits 
18-35. Optional hardware is available for byte manipulation - a byte is any 
contiguous set of bits within a word. Registers that hold addresses have 
eighteen bits, numbered 18-35 according to the position of the address in a 
word. Words are used either as computer instructions in the program, as 
addresses, or as operands (data for the program). 

Of the internal registers shown in the illustration on the next page, only 
PC, the 18 bit program counter, is directly relevant to the programmer. The. 
processor performs a program by executing instructions retrieved from the 
locations addressed by PC. At the beginn'"'^ of each instruction PC is incre- 
mented by one so that it normally contains an address one greater than the 
location of the current instruction. Sequential program flow is altered by 
changing the contents of PC, either by incrementing it an extra time in a 
skip instruction or by replacing its contents with the value specified by a 
jump instruction. Also of importance to the programmer is the 36-bit data 
switch register DS on the processor console: through this register the pro- 
gram can read data supplied by the operator. The processor also contains 
flags that detect various types of errors, including several types of overflow 
in arithmetic and pushdown operations, and provide other information of 
interest to the programmer. 

The processor has other registers but the programmer is not usually con- 
cerned with them except when manually stepping through a program to 
debug it. By means of the address switch register AS, the operator can 

1-1 



1-2 



/ 














INTRODUCTION 




















■■ 


CORE MEMORY 

8192 OR 16384 
37-BIT WORDS 




CORE MEMORY 




CORE MEMORY 








1 










t 











MEMORY BUS 


CENTRAL 




i 


\ 


- 






PROCESSOR 






r- 


FAST 
" MEMORY 

16X3€ 




' ' 1 












r 




i 






MA 

18 




ARITHMETIC 
LOGIC 

(AR, BR, MQ) 




IR 

18 










i 


\ 


1 










_ 




Ml 

36 










f 












AS 

18 


PC 

18 


1 , 




DS 

36 




1 . 


^ 




IN-OU 


T-^BUS 


1 












1 


* 











i 
1 


\ 




1 




1 






n ' ' 






PRIORITY 
INTERRUPT 




PAPER TAPE 
READER 




PAPER TAPE 
PUNCH 




TELETYPE 





PDP-iO SIMPLIFIED 



examine the contents of, or deposit information into, any memory location; 
stop or interrupt the program whenever a particular location is referenced; 
and through AS the operator can supply a starting address for the program. 
Through the memory indicators MI the program can display data for the 
operator. The instruction register IR contains the left half of the current 
instruction word, ie all but the address part. The memory address register 
MA supplies the address for every memory access. The heart of the proc- 
essor is the arithmetic logic, principally the 36-bit arithmetic register AR. 



1-3 



This register takes part in all arithmetic, Iqgical and data handling operations; 
all data transfers to and from memory, peripheral equipment and console are 
made via AR. Associated with AR are an extremely fast full adder, a buffer 
register BR that holds a second operand in many arithmetic and logical 
instructions, a multiplier-quotient register MQ that Serves primarily as an 
extension of AR for handling double length operands, and smaller registers 
that handle floating point exponents and control shift operations and byte 
manipulation. 

From the point of view of the programmer however the arithmetic logic 
can be regarded as a black box. It performs almost all of the operations 
necessary for the execution of a program, but it never retains any informa- 
tion from one instruction to the next. Computations performed in the black 
box either affect control elements such as PC and the flags, or produce 
results that are always sent to memory and must be retrieved by the proc- 
essor if they are to be used as operands in other instructions. 

An instruction word has only one 18-bit address field for addressing any 
location throughout all of memory. But most instructions have two 4-bit 
fields for addressing the first sixteen memory locations. Any instruction 
that requires a second gperand has an accumulator address field, which can 
address one of these sixteen locations as an accumulator; in other words as 
though it were a result held over in the^ processor from some previous 
instruction (the programmer usually has a choice of whether the result of the 
instruction will go to the location addressed as an accumulator or to that 
addressed by the 18-bit address field, or to both). Every instruction has a 
4-bit index register address field, which can address fifteen of these locations 
for use as index registers in modifying the 18-bit memory address (a zero 
index register address specifies no indexing). Although all computations on 
both operands and addresses are performed in the single arithmetic register 
AR, the computer actually has sixteen accumulators, fifteen of which can 
double as index registers. The factor that determines whether one of the 
first sixteen locations in memory is an accumulator or an index register is 
not the information it contains nor how its contents are used, but rather 
how the location is addressed. There need be no difference physically be- 
tween these locations and other memory locations, but an optional, fast flip- 
flop memory contained in the processor can be substituted for the bottom 
sixteen locations in core. This allows much quicker access to these locations 
whether they are addressed as accumulators, index registers or ordinary 
memory locations. They can even be addressed from the program counter, 
gaining faster execution for a short but oft-repeated subroutine. 

Besides the registers that enter into the regular execution of the program 
and its instructions, the processor has a priority interrupt system and can 
contain optional equipment to facilitate time sharing. The interrupt system 
facihtates processor control of the peripheral equipment by means of a num- 
ber of priority-ordered channels over which external signals may interrupt 
ttie normal program flow. The processor acknowledges an interrupt request 
by executing the instruction contained in a particular location assigned to 
the channel. Assignment of channels to devices is entirely under program 
control. One of the devices to which the program can assign a channel is the 
processor itself, allowing internal conditions such as overflow or a parity 



1-4 



10 . 

INTRODUCTION §1.1 

error to" signal the program. 

The time share hardware provides memory protection and relocation. 
Without time sharing, all instructions and all memory are available to the 
program. Otherwise a number of programs share processor time, with each 
program relocated and restricted to a specific area in core, and certain in- 
structions are usually illegal. An attempt by any user j;o execute an illegal 
instruction or address a memory location outside of his area results in a 
transfer of control back to the time-sharing monitor. 



1-1 NUMBER SYSTEM 

The program can interpret a data word as a 36-digit, unsigned binary num- 
ber, or the left and right halves of a word can be taken as separate 18-bit 
numbers. The PDP-10 repertoire includes instructions that effectively add 
or subtract one from both halves of a word, so the right half can be used for 
address modification when the word is addressed as an index register, while 
the left half is used to keep a control count. 

The standard arithmetic instructions in the PDP-10 use twos comple- 
ment, fixed point conventions to do binary arithmetic. In a word used as a 
number, bit (the leftmost bit) represents the sign, for positive, 1 for 
negative. In a positive number the remaining 35 bits are the magnitude in 
ordinary binary notation. The negative of a number is obtained by taking its 
twos corriplement. If x is, an w-digit binary number, its twos complement is 
2" - X, and its ones complement is(2"-l)-x,or equivalently (2" - x) - 1 . 
Subtracting a number from 2"- 1 (ie, from all Is) is equivalent toperform- 
mg-the logical complement, ie changing all Os to Is and all Is to Os. There- 
fore, to form the twos complement one takes the logical complement 
(usually referred to merely as the complement) of the entire word including 
the sign, and adds 1 to the result. In a negative number the sign bit is 1, and 
the remaining bits are the twos complement of the magnitude. 



+ 153io = +2318 = 000 000 000 000 000 000 000 000 000 010 011001 



35 



-153,0 = -231 



111 111 111 111 111 111 111 111 111 101 100 111 



Zero is represented by a word containing all Os. Complementing this num- 
ber produces all 1 s, and adding 1 to that produces all Os again. Hence there 
is only one zero representation and its sign is positive. Since the numbers are 
symmetrical in magnitude about a single zero representation, all even num-'' 
bers both positive and negative end in 0, all odd numbers in 1 (a number all 
Is represents -1). But since there are the same number of positive and nega- 
tive numbers and zero is positive, there is one more negative number than 
there are nonzero positive numbers. This is the most negative number and it 
cannot be produced by negating any positive number (its octal representa- 



11 



§1.1 



NUMBER SYSTEM 



1-5 



tion is 400000 OOOOOOg and its magnitude is one greater than the largest 
positive number). 

If ones complements were used for negatives one could read a negative 
number by attaching significance to the Os instead of the Is. In twos com- 
plement notation each negative number is one greater than the complement 
of the positive number of the same magnitude, so one can read a negative 
number by attaching significance to the rightmost 1 and attaching signifi- 
cance to the Os at the left of it (the negative number of largest magnitude has 
a 1 in only the sign position). In a negative integer, Is may be discarded at 
the left, just as leading Os may be dropped in a positive integer. In a negative 
fraction, Os may be discarded at the right. So long as only Os are discarded, 
the number remains in twos complement form because it still has a 1 that 
possesses significance; but if a portion including the rightmost 1 is discarded, 
the remaining part of the fraction is now a ones complement. 

The computer does not keep track of a binary point — the programmer 
must adopt a point convention and shift the magnitude of the result to con- 
form to the convention used. Two common conventions are to regard a 
number as an integer (binary point at the right) or as a proper fraction 
(binary point at the left); in these two cases the range of numbers repre- 
sented by a single word is -2^^ to 2^^ - 1 or -1 to 1 - 2"^^. Since multiplica- 
tion and division make use of double length numbers, there are special 
instructions for performing these operations with integral operands. 

Floating Point Arithmetic. Optional PDP- 10 hardware is available for 
processing floating point numbers. A floating point instruction interprets 
bit of a word as the sign, but interprets the rest of the word as an 8-bit 
exponent and a 27-bit fraction. For a positive number the sign is 0, as 
before. But the contents of bits 9-35 are now interpreted only as a binary 
fraction, and the contents of bits 1-8 are interpreted as an integral exponent 
in excess 128 (2008) code. Exponents from —128 to +127 are therefore 
represented by the binary equivalents of to 255 (0-3778). Floatingpoint 
zero and negatives are represented in exactly the same way as in fixed point: 
zero by a word containing all Os, a negative by the twos con^plement. A 
negative number has a 1 for its sign and the twos complement of the frac- 
tion, but since every fraction must ordinarily contain a 1 unless the entire 
number is zero (see below), it has the ones complement of the exponent 
code in bits 1-8. Since the exponent is in excess 128 code, an actual 
exponent x is represented in a positive number by ;»f -f- 128, in a negative 
number by 127 -jc. The programmer, hov/^ver, need not be concerned with 
these representations as the hardware compensates automatically. Eg, for 



Multiplication produces a 
double length product, and 
the programmer must remem- 
ber that discarding the low 
order part of a double length 
negative leaves the high order 
part in correct twos comple- 
ment form only if the low 
order part is null. 



-hl53 



10 



+2318 = +.4628 X2« 



10 001 000 100 1 10 010 000 000 000 000 000 000 



1 



8 9 



35 



-J 53 



10 



■231r = -A62.X2^ = 



101 110 Ml Oil 001 110 000 000 000 000 000 000 



8 9 



35 



1-6 



12 

INTRODUCTION 



§1.2 



the instruction that scales the exponent, the hardware interprets the integral 
scale factor in standard twos complement form but produces the correct 
ones complement result for the exponent. 

Except in special cases the floating point instructions assume that all non- 
zero operands are normalized, and they normalize a nonzero result. A 
floating point number is considered normalized if the magnitude of the frac- 
tion is greater than or equal to Vi and less than 1 . These numbers thus have a 
fractional range in magnitude of Vi to 1 - 1"^"^ and an exponent range of 
- 1 28 to +127. The hardware may not give the correct result if the program 
supplies an operand that is not normalized or that has a zero fraction with a 
nonzero exponent. 

The precaution about truncation given for fixed point multiplication 
applies to all floating point operations as they all produce extra length 
results; but here the programmer may request rounding, which automatically 
restores the high order part to twos complement form if it is negative. In 
division the two words of the result are quotient and remainder, but in the 
other operations they form a double length number which is stored in two 
accumulators if the instruction is executed in "long" mode. This number 
contains a 54-bit fraction, half of which is in bits 9-35 of each word. The 
sign and exponent are in bits and 1 -8 respectively of the word containing 
the more significant half, and the standard twos complement is used to form 
the negative of the entire 63-bit string. In the remaining part of the less 
significant word, bit is 0, and bits 1-8 contain a number 27 less than the 
exponent, but this is expressed in positive form even though bits 9-35 may. 
be part of a negative fraction. Eg the number 2*^-1- 2"** has this two-word 
representation: 



10010011 



100 000 000 000 000 000 000 000 000 



001 111 000 



000 000 000 100 poo 000 000 000 000 



35 



whereas its negative is 



01 101 100 



oil 111 111 111 111 111 111 111 111 



8 9 



35 



001 111 000 



111 111 111 100 000 000 000 000 000 



89 



35 



1.2 INSTRUCTION FORMAT 



In all but the input-output instructions, the nine high order bits (0-8) speci- 
fy the operation, and bits 9-12 usually address an accumulator but are 
sometimes used for special control purposes, such as addressing flags. The 



13 



§1.2 



INSTRUCTION FORMAT 



i-7 



rest of the instruction word usually supplies information for calculating the 
effective address, which is the actual address used to fetch the operand or 
alter program flow. Bit 13 specifies the type of addressing, bits 14-17 spec- 
ify an index register for use in address modification, and the remaining 
eighteen bits (18-35) address a memory location. The instruction codes 



ADDRESS TYPE 



ACCUMULATOR 
ADDRESS V 



INDEX REGISTER 
/ ADDRESS 



INSTRUCTION CODE 



MEMORY ADDRESS 



89 12 13 14 17 18 

BASIC INSTRUCTION FORMAT 



35 



that are not assigned as specific instructions are executed by the processor 
as so-called "unimplemented operations", as are the codes for floating point 
and byte manipulation in any PDF- 10 that does not have the optional hard- 
ware for these instructions. When the processor encounters one of these 
unimplemented codes in a program, it stores bits 0-12 of the instriiction 
word and the calculated effective address in a particular memory location 
and then executes the instruction contained in a second location. 

An input-output instruction is designated by three Is in bits 0-2. Bits 
3-9 address the in-out device to be used in executing the instruction, and 
bits 10-12 specify the operation. The rest of the word is the same as in 
other instructions. 



^ 



INSTRUCTION, 
CODE 



ADDRESS TYPE 



INDEX REGISTER 
/ ADDRESS 



DEVICE CODE 



MEMORY ADDRESS 



23 



9 10 12 13 14 17 18 

IN-OUT INSTRUCTION FORMAT 



35 



Effective Address Calculation. Bits 13-35 have the same format in every 
instruction whether it addresses a memory location or not. Bit 13 is the 



13 14 



17 18 



35 



indirect bit, bits 14-17 are the index register address, and if the instruction 
must reference memory, bits 18-35 are the memory address Y, The effec- 
tive address E of the instruction depends on the values of/, X and Y. If ^ is 
nonzero, the contents of index register X are added to Y to produce a modi- 
fied address. If / is 0, addressing is direct, and the modified address is the 
effective address used in the execution of the instruction; if / is 1 , addressing 
is indirect, and the processor retrieves another address word from the loca- 
tion specified by the modified address already determined. This new word is 
processed in exactly the same manner: X and Y determine the effective ad- 
dress if / is 0, otherwise they are used for yet another level of address 



14 

1-8 INTRODUCTION §1.3 

retrieval. This process continues until some referenced location is found 
with a in bit 13; the 18-l)it number calculated from the X and Y parts of 
this location is the effective address E. 

The calculation outlined above is carried out for every instruction even 
if it need not address a memory location. If the indirect bit in the instruc- 
tion word is and no memory reference is necessaty, then Y is not an ad- 
dress. It may be a mask in "some kind of test instruction, conditions to be 
sent to an in-out device, or part of it may be the number of places to shift in 
a shift or rotate instruction or the scale factor in a floating scale instruction. 
Even when modified by an index register, bits 18-35 do not contain an ad- 
dress when / is 0. But when / is 1 , the number determined from bits 14-35 
is an indirect address no matter what type of information the instruction 
requires, and the word retrieved in any step of the calculation contains an 
indirect address so long as / remains 1 . When a location is found in which / 
is 0, bits 18-35 (perhaps modified by an index register) contain the desired 
effective mask, effective conditions, effective shift number, or effective scale 
factor. ' Many of the instructions that usually reference memory for an oper- 
and even have an "immediate" mode in which the result of the effective 
address calculation is itself used as a half word operand instead of a word 
taken from the memory location it addresses. 

The important thing for the programmer to remember is that the same 
calculation is carried out for every instruction regardless of the type of infor- 
mation that must be specified for its execution, or even if the result is 
ignored. In the discussion of any instruction, E refers to the actual quantity 
derived from /, X and Y and used in the execution of the instruction, be it 
the entire half word as in the case of an address, immediate operand, mask or 
conditions, or only part of it as in a shift number or scale factor. 



1.3 MEMORY 

All timing in the PDP-10 is asynchronous. The internal timing for each in- 
out device and each memory is entirely independent of the central processor. 
Because core meniory readout is destructive, every word read must be writ- 
ten back in unless new information is to take its place. The basic read-write 
cycle time of the standard core memory is either 1.00 or 1.65 microseconds, 
but the processor need never wait the entire cycle time. To read, it waits 
only until the information is available and then continues its operations 
while the memory performs the write portion of the cycle; to write, it waits 
only until the data is accepted, and the memory then performs an entire 
cycle to clear and write. To save time in an instruction that fetches an oper- 
and and then writes new data into the same location, the memory executes a 
read-pause- write cycle in which it performs only the read part initially and 
then completes the cycle when the processor suppHes the new data. 

Access times for the accumulator-index register locations are decreased 
considerably by substitution of a fast memory (contained in the processor) 
for the first sixteen core locations. Readout is nondestructive, so the fast 
memory has no basic cycle: the processor reads a word directly, but to write 



15 



§1.3 



MEMORY 



1-9 



it must first clear the location and then load it. Access times in nanoseconds 
(including 20 feet of cable delay) for the three memories are as follows. 



MA 1 or MA 1 OA Core Memory ( i .00 ms) 

MB 1 Core Memory ( 1 .65 /zs) 

KM 1 Fast Memory ( 1 8-bit address) 



Read 
580 

600(700)* 
210 



Write 

200 

200 (300) 

210 



Note: When a fast memory location is addressed as an accumulator or index 
register, the access time is usually considerably shorter than that listed here. 

From the simple addressing point of view, the entire memory is a set of 
contiguous locations whose addresses range from zero to a maximum 
dependent upon the capacity of the particular installation. In a system with 
the greatest possible capacity, the largest address is octal 777777, decimal 
262,143. (Addresses are always in octal notation unless otherwise specified.) 
But the whole memory would usually be made up of a number of core mem- 
ories each having a capacity of 8192 or 16,384 words. Hence a single 18-bit 
address actually selects a particular memory and a specific location within it. 
For an 8K memory the high order five address bits select the memory, the 
remainmg thirteen bits address a single location in it; selecting a 16K 
memory takes four bits, leaving fourteen for the locationi The times given 
above assume the addressed memory is idle when access is requested. To 
avoid waiting for a previously requested memory cycle to end, the program 
can make consecutive requests to different memories by taking instructions 
from one memory and data from another. The hardware also allows pairs 
of memories to be interleaved in such a way that consecutive addresses 
actually alternate between the two memories in the pair (thus increasing the 
probability that consecutive references are to different niemories). Appro- 
priate switch settings at the memories interchange the least significant 
address bits in the memory and location parts, so that in any two memories 
numbered n and n + 1 where /i is even, all even addresses are locations in the 
first memory, all odd addresses are locations in the second. Hence memories 
and 1 can be interleaved as can 6 and 7, but not 3 and 4 or 5 and 7. 

Memory Allocation. The use of certain memory locations is defined by 
the hardware. 





0-17 

1-17 

40-41 

42-57 

60-61 



140-161 



Holds a pointer word during a bootstrap readin 

Can be addressed as accumulators 

Can be addressed as index registers 

Trap for unimplemented user operations (UUOs) 

Priority interrupt locations 

Trap for remaining unimplemented operations: these include 
the unassigned instruction codes that are reserved for future 
use, and also the byte manipulation and floating point instruc- 
tions when the hardware for them is not installed 

Allocated to second processor if connected (same use as 40-61 
for first processor) 



*Numbers in parentheses are 
the longer times required in 
a multiprocessor system. 



All information given in this 
manual about memory loca- 
tions 40-61 applies instead 
to locations 140-161 for pro- 
gramming a second central 
processor connected to the 
same memory. 

The initial control word 
address for the DP 10 Data 
Channel must be less than 
1000. 



AUGUST 1969 



1-10 



16 

INTRODUCTION 



§1.4 



The assembler translates 
every statement into a 36-bit 
word, placing Os in all bits 
whose values are unspecified. 



1.4 PROGRAMMING CONVENTIONS 

The computer has five instruction classes: data transmission, logical, arith- 
metic, program control and in-out. The instructions in the in-out class con- 
trol the peripheral equipment, and also control the priority interrupt and 
time sharing, control and read the processor flags, and communicate with the 
console. The next chapter descri)>es all instructions mentioned above, 
presents a general description of input-output, and describes the effects of 
the in-out instructions on the processor, priority interrupt and time share 
hardware. Effects of in-out instructions on particular peripheral devices are 
discussed with the devices. 

The Macro -10 assembly program recognizes a number of mnemonics and 
other initial symbols that facilitate constructing complete instruction words 
and organizing them into a program. In particular there are mnemonics for 
the instruction codes (Appendix A), which are six bits m in-out instructions, 
otherwise nine or thirteen bits. Eg the mnemonic 

MOVNS 

assembles as 213000 000000, and 

. MOVNS 2570 

assembles" as 213000 002570. This latter word, when executed as an instruc- 
tion, produces the twos complement negative of the word in memory loca- 
tion 2570. '^ 

Note 

Throughout this ^manual all numbers representing instruction words, 
register contents, codes and addresses are always octal, and any num- 
bers appearing in program examples are octal unless otherwise indi- 
cated. On the other hand, the ordinary use of numbers in the text to 
count steps in an operation or to specify word or byte lengths, bit 
positions, exponents, etc employs standard decimal notation. 



The initial symbol @ preceding a memory address places a 1 in bit 13 to 
produce indirect addressing. The example given above uses direct addressing, 

but 

MOVNS @2570 

assembles as 213020 002570, and produces indirect addressing. Placing the 
number of an index register (1-17) in parentheses following the memory 
address causes modification of the address by the contents of the specified 
register. Hence 

MOVNS @2570(12) 

which assembles as 213032 002570, produces indexing using index register 
12, and the processor then uses the modified address to continue the effec- 
tive address calculation. ^ 

An accumulator address (0-17) precedes the memory address part (if any) 



17 

§1.4 PROGRAMMING CONVENTIONS 1-11 

and is terminated by a comma. Thus 

MOVNS 4,@2570(12) 

assembles as 213232 002570, which negates the word in location E and 
stores the result in both E and in accumulator 4. The same procedure may 
be used to place Is in bits 9-12 when these are used for something other 
than addressing an accumulator, but mnemonics arfe available for this pur- 
pose. 

The device code in an in-out instruction is given in the same manner as an 
accumulator address (terminated by a comma and preceding the address 
part), but the number given must correspond to the octal digits in the word 
(000-774). Mnemonics are however available for all standard device codes. 
To control the priority interrupt system whose code is 004, one may give 

CONO 4,1302 

which assembles as 700600 001302, or equivalently a 

CONO PI, 1302 

The programming examples in this manual use the following addressing 
conventions: 

♦ A colon following a symbol indicates that it is a symbolic location name. 

A: ADD 6,5704 

indicates that the location that contains ADD 6,5704 may be addressed sym- 
bolically as A. 

♦ The period represents the current address, eg 

ADD 5, .+2 
is equivalent to 
A: ADD 5,A+2 

♦ Square brackets specify the content: of a location, leaving the address of 
the location implicit but unspecified. Eg 

ADD 12,[ 72560041 

and * 

ADD 12, A 



A: 7256004 

are equivalent. 

Anything written at the right of a semicolon is commentary that explains 
the program but is not part of it. 



AUGUST 1969 



Central Processor 



This chapter describes all PDP-10 instructions but does not discuss the 
effects of those in-out instructions that address specific peripheral devices. 
In the description of each instruction, the mnemonic and name are at the 
top, the format is in a box below them. The mnemonic assembles to the 
word in the box, where bits in those parts of the word represented by letters 
assemble as Os. The letters indicate portions that must be added to the mne- 
monic to produce a complete instruction word. 

For many of the non-IO instructions, a description applies not to a unique 
instruction with a single code in bits 0-8, but rather to an instruction set 
defined as a basic instruction that can be executed in a number of modes. 
These modes define properties subsidiary to the basic operation; eg in data 
transmission the mode specifies which of the locations addressed by the in- 
struction is the source and which the destination of the data, in test instruc- 
tions it specifies the condition that must be satisfied for a jump or skip to 
take place. The mnemonic given at the top is for the basic mode; mnemonics 
for the other forms of the instruction are produce^ by appending letters 
directly to the basic mnemonic. Following the description is a table giving 
the mnemonics and octal codes (bits 0-8) for the various modes. 

The processor execution time for each instruction is also given at the top 
unless the time differs from one mode to another. The time listed is that 
required for direct addressing without indexing (ie with no effective address 
calculation), assuming the instruction and location E are both in the same 
1.00 microsecond core memory, and that an accumulator is addressed only 
if necessary and is in fast memory. The time that can be saved (if any) by 
interieaving or keeping instructions and operands in different memories is 
indicated either with the description oi- with the discussion of the modes 
preceding a group of instructions. To determine the exact time required for 
an instruction under any circumstances, refer to the timing chart in 
Appendix C. 

In a description E refers to the effective address, half word operand, mask, 
conditions, shift number or scale factor calculated from the /, X and Y parts 
of the instruction word. In an instruction that ordinarily references mem- 
ory, a reference to E as the source of information means that the instruction 
retrieves the word contained in location £"; as a destination it means the in- 
struction stores a word in location E. In the immediate mode of these 
instructions, the effective half word operand is usually treated as a full word 
that contains E in one half and zero in the other, and is represented either as 
0,E or E,0 depending upon whether E is in the right or left half. 



Letters representing modes 
are suffixes, which produce 
new mnemonics that are rec- 
ognized as distinct symbols 
by the assembler. 



The times listed should be re- 
garded as good approxima- 
tions. For more exact times 
with the conditions given here 
(ie 1.00 microsecond core, 
etc) add 60 nanoseconds to 
the listed time, plus an addi- 
tional 30 nanoseconds for 
each core memory access for 
retrieval of an operand and 
another 30 nanoseconds if 
the instruction does not write 
a result in core. 



2-1 ' 



AUGUST 1969 



20 

2-2 CENTRAL' PROCESSOR §2,1 

Most of the non-IO instructions can address an accumulator, and in the 

box showing the format this address is represented by ^; in the description, 

/ "AC*' refers to the accumulator addressed by A . "AC left" and "AC right" 

refer to the two halves of AC. If an instruction uses two accumulators, these 
have addresses A and ^ + 1, where the second address is if ^ is 17. In some 
cases an instruction uses an accumulator only if ^ is nonzero: a zero address 
,in bits 9-12 specifies no accumulator. 

It is assumed throughout that time sharing is not in effect, and the pro- 
gram is unrestricted. For completeness, however, the effects of restrictions 
on particular instructions are noted ; and execution times are given both for 
unrestricted operation and including relocation in a user program (the latter 
time is given in parentheses). §2.15 lists all restrictions on user programs 
and explains the special effects produced by certain instructions when exe- 
cuted under control of the monitor while the processor is in user mode. 

Some simple examples are included with the instruction descriptions, but 
more complex examples using a variety of instructions are given in § 2. 1 1 . 



2.1 HALF WORD DATA TRANSMISSION 

These instructions move a half word and may modify the contents of the 
other half of the destination location. There are sixteen instructions deter- 
mined by which half of the source word is moved to which half of the des- 
tination, and by which of four possible operations is performed on the other 
half of the destination. The basic mnemonics are three letters that indicate 
the transfer 

HLL Left half of soured to left half of destination 

HRL Right half of source to left half of destination 

HRR Right half of source to right half of destination 

HLR Left half of source to right half of destination 

plus a fourth, if necessary, to indicate the operation. 

i 
Operation Suffix Effect on Other Half of Destination 

None 

Places Os in all bits of the other half 

Places Is in all bits of the other half 

Places the sign (the leftmost bit) of 
the half word moved in all bits of the 
other half. This action extends a right 
half word number into a full word 
number but is valid arithmetically 
only for positive left half word num- 
bers - the right extension of a number 
requires Os regardless of sign (hence 
the Zeros operation should be used to 
extend a left half word number). 



Do nothing 




Zeros 


Z 


Ones 





Extend 


E 



§2-1 



21 



HALF WORD DATA TRANSMISSION 



2-3 



An additional letter may be appended to indicate the tnode, which deter- 
mines the source and destination of the half word moved. 



Mode 


Suffix 


Source 


Destination 


Basic 




E 


AC 


Immediate 


I 


The word 0,£ 


AC 


Memory 


M 


AC 


E 


Self 


S 


E 


E, but also AC 
if A is nonzero 



Note that selecting the left half of the source in immediate mode merely 
clears the selected half of the destination. 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) jUS in self 
mode; in memory mode the 
s^me saving results if no ac- 
tion is taken on the other 
half, otherwise .47 (.36) jUS 
is saved. 

When E addresses a fast 
memory location, a half word 
transfer takes .34 /is less in 
basic mode, either* .46 (.35) 
or .54 (.43) /us less in memory 
mode depending respectively 
on whether or not any action 
is taken on the other half, 
and .54 (.43) ais less in self 
mode. 



HLL 



Half Word Left to Left 



500 


M 


A 


I 


X 


Y 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination.^ The source and the destination right half are un- 
affected; the original contents of the destination are lost. 



HLL 


Half Left to Left 


500 


2.35 (2.57) MS 


HLLI 


Half Left to Left Immediate 


501 


1.50 (1.61) MS 


HLLM 


Half Left to Left Memory 


502 


2.90 (3.01) MS 


HLLS 


Half Left to Left Self 


503 


2.76 (2.87) MS 



HLLI merely clears AC left. 
If A is zero, HLLS is a no-op, 
otherwise it is equivalent to 
HLL. 



HLLZ 



Half Word Left to Left, Zeros 



510 


M 


A 


I X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination, and clear the destmation right half. The source is un- 
affected, the original contents of the destination are lost. 



HLLZ Half Left to Left, Zeros 

H LLZI Half Left to Left, Zeros, Immediate 

H LLZM Half Left to Left, Zeros, Memory 

HLLZS Half Left to Left, Zeros, Self 



510 
2.21 (2.43) MS 

511 
1.36 (1.47) MS 

512 
2.47 (2.58) MS 

513 
2.76 (2.87) MS 



HLLZ! merely clears AC. If ^ 
is zero, HLLZS merely clears 
the right half of location E. 



22 



2-4 



HLLOI sets AC to all Os in 
the left half, all Is in the 
right. 



HLLO 



CENTRAL PROCESSOR 



Half Word Left to Left, Ones 



§2J 



520 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



Move the left half of the source word specified by M to the 
specified destination, and set the destination right half to all 
is unaffected, the original contents of the destination are lost. 

HLLO Half Left to Left, Ones / 

HLLOI Half Left to Left, Ones, Immediate 

HLLOM Half Left to Left, Ones, Memory 

HLLOS Half Left to Left, Ones, Self 



35 

left half of the 
Is, The source 

520 

2.21 (2.43) MS 

521 

1.36 (1.47) MS 
522 

2.47 (2.58) MS 
523 

2.76 (2.87) MS 



HLLEf is equivalent to 
HLLZI (it merely clears AC). 



HLLE 



Half Word Left to Left, Extend 



5 30 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the left half of the 
specified destination, and make all bits in the destination right half equal to 
bit of the source. The source is unaffected, the original contents of the 
destination are lost. 



HLLE Half Left to Left, Extend 

HLLE! Half Left to Left, Extend, Immediate 

HLLEM Half Left to Left, Extend, Memory 

HLLES Half Left to Left, Extend, Self 



530 
2.21 (2.43) MS 

531 
1.36 (1.47) MS 

532 
2.47 (2.58) MS 

533 
2.76 (2.87) MS 



HRL 



Half Word Right to Left 



504 


M 


A 


I 


^ 


Y 



67 8' 



12 13 14 



1718 



35 



Move the right half of the source word specified by M to the left half of the 
specified destination. The source -and the destination right half are unaf- 
fected; the original contents of the destination left half are lost. 



HRL 


Half Right to Left 


504 


2.70 (2.92) MS 


HRLI 


Half Right to Left Immediate 


505 


1.85 (1.96) MS 



§2.1 

HRLM 
HRLS 



23 



HALF WORD DATA TRANSMISSION 



Half Right to Left Memory 
Half Right to Left Self 



506 
507 



2.90 (3.01) MS 
2.76 (2.87) MS 



2-5 



HRLZ 



Half Word Right to Left, Zeros 



5 14 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



35 



Move Ijhe right half of the source word specified by M to the left half of the 
specified destination, and clear the destination right half. The spurce is un- 
affected, the original contents of the destination are lost. 



HRLZ Half Right to Left, Zeros 

HRLZI Half Right to Left, Zeros, Immediate 

H R LZM Half Right to Left, Zeros, Memory 

HRLZS HalfRighttoLeft, Zeros, Self 



514 
2.21 (2.43) MS 

515 
1.36 (1.47) MS 

516 
2.47 (2.58) MS 

517 
2.76 (2.87) MS 



HRLZI loads the word £',0 
into AC. 



HRLO 



524 



Half Word Right to Left, Ones 



M 



12 13 14 



1718 



Move the right half of the source word specified by M to the 
specified destination, and set the destination right half to all 
is unaffected, the original contents of the destination are lost. 

HRLO Half Right to Left, Ones 

HRLO I Half Right to Left, Ones, Immediate 

HRLOM Half Right to Left, Ones, Memory 

H R LOS Half Right to Left, Ones, Self 



35 

left half of the 
Is. The source 

524 
2.21 (2.43) MS 

525 
1.36 (1.47) MS 

526 
2.47 (2.58) MS 

527 
2.76 (2.87) MS 



HRLE 



Half Word Right to Left, Extend 



534 



M 



6 7 89 12 13 14 17 18 35 

Move the right half of the source word specified by M to the left half of the 



2-6 



24 



CENTRAL PROCESSOR 



§11 



specified destination, and make all bits in the destination right half equal to 
bit 1 8 of the source. The source is unaffected, the original contents of the 
destination are lost. 



HRLE Half Right to Left, Extend 

HRLEI Half Right to Left, Extend, Immediate 

H R LEM Half Right to Left, Extend, Memory 

HRLES Half Right to Left, Extend, Self 



534 
2.21 (2.43) MS 

535 
1.36 (1.47) MS 

536 
2.47 (2.58) MS 

537 
2.76 (2.87) MS 



If A is zero, HRRS is a no-op; 
otherwise it is equivalent to 
HRR. 



HRR 



Half Word Right to Right 



540 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination. The source and the destination left half are unaffected; 
the original contents of the destination right half are lost. 

HRR Half Right to Right 540 2.35 (2.57) ms 

HRRI Half Right to Right Immediate 541 1.50 (1.61) ms 

HRRM Half Right to Right Memory 542' 2.90 (3.01) ms 

HRRS Half Right to Right Self 543 2.76 (2.87) ms 



HRRZI loads the word O.^" 
into AC. If ^ is zero, HRRZS 
merely clears the left half of 
location E. 



HRRZ 



Half Word Right to Right, Zeros 



550 


M 


A I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination, and clear the destination left half. The source is unaf- 
fected, the original contents of the destination are lost. 



HRRZ Half Right to Right, Zeros 

HRRZI Half Right to Right, Zeros, Immediate 

HRRZM Half Right to Right, Zeros, Memory 

HR RZS Half Right to Right. Zeros, Self 



550 
2.21 (2.43) MS 

551 
1.36 (1.47) MS 

552 
2.47 (2.58) MS 

553 
2.76 (2.87) MS 



§2.1 



HALF WORD DATA TRANSMISSION 



2-7 



HRRO 



Half Word Right to Right, Ones 



560 



M 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination, and set the destination left half to all 1 s. The source is 
unaffected, the original contents of the destination are lost. 



HRRO Half Right to Right, Ones 

HRROI Half Right to Right, Ones, Immediate 

HRROM Half Right to Right, Ones, Memory 

HRROS Half Right to Right, Ones, Self 



560 
2.21 (2.43) /xs 

561 
1.36 (1.47) MS 

562 
2.47 (2.58) MS 

563 
2.76 (2.87) MS 



HRRE Half Word Right to Right, Extend 



570 



M 



67 89 



12 13 14 



17 18 



35 



Move the right half of the source word specified by M to the right half of the 
specified destination, and make all bits in the destination left half equal to 
bit 18 of the source. The source is unaffected, the original contents of the 
destination are lost. 



HRRE Half Right to Right, Extend 

HRREI Half Right to Right, Extend, Immediate 

H R R EM Half Right to Right, Extend, Memory 

HRRES Half Right to Right, Extend, Self 



570 
2.21 (2.43) MS 

571 
1.36 (1.47) MS 

572 
2.47 (2.58) MS 

573 
2.76 (2.87) MS 



HLR 



ffalf Word Left to Right 



544 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination. The source and the destination left half are unaffected; 
the original contents of the destination right half are lost. 

Half Left to Right 544 2.70 (2.92) ms 



HLR 



HLRI 



Half Left to Right Immediate 



545 



1 .85 ( 1 .96) MS HLRI merely clears AC right. 



26 



2-8 



CENTRAL PROCESSOR 



HLRM Half Left to Right Memory 

HLRS Half Left to Right Self 



546 

547 



§2.1 

2.90 (3.01) MS 
2.76 (2.87) MS 



HLRZI merely clears AC and 
is thus equivalent to HLLZI. 



HLRZ 



Half Word Left to Right, Zeros 



554 


M 


A 


I 


X 


■ y 



67 89 



17 18 



Move the left half of the source word specified by M to the right half of the 
specified destination, and clear the destination left half. The source is un- 
affected, the original contents of the destination are lost. 



HLRZ Half Left to Right, Zeros 

HLRZI Half Left to Right, Zeros, Immediate 

HLRZM Half Left to Right, Zeros, Memory 

H L RZS Half Left to Right, ZeroS, Self 



554 
2.21 (2.43) MS 

555 
1.36 (1.47) MS 

556 
2.47 (2.58) MS 

557' 
2.76 (2.87) MS 



HLROI sets AC to all is in 
the left half, all Os in the 
right. 



HLRO 



Half Word Left to Right, Ones 



5-64 


M 


A 


I 


X 


Y 



6 7 8 9 



17 18 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination, and set the destination left half to all Is. The source is 
unaffected, the original contents of the destination are lost. 

Half Left to Right, Ones 564 

2.21 (2.43) MS 
Half Left to Right, Ones, Immediate 565 

1.36 (1.47) MS 
Half Left to Right, Ones, Memory 566 

2.47 (2.58) MS 
Half Left to Right, Ones, Self ^ 567 

2.76 (2.87) MS 



HLRO 
HLROI 
HLROM 
HLROS 



HLRE 



Half Word Left to Right, Extend 



574 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



35 



Move the left half of the source word specified by M to the right half of the 
specified destination, and make all bits in the destination left half equal to 



27 



§2.2 



FULL WORD DATA TRANSMISSION 



bit of the source. The source is unaffected, the original contents of the 
destination are lost. 



HLRE Half Left to Right, Extend 

HLREI Half Left to Right, Extend, Immediate 

HLREM Half Left to Right, Extend, Memory 

H L R ES Half Left to Right, Extend, Self 



,574 

2.21 (2.43) MS 

575 

1.36 (1.47) /is 

576 
2.47 (2.58) /xs 

577 
2.76 (2.87) ^ls 



2-9 



HLREI is equivalent tc 
HLRZI (it merely clears AC). 



Examples. The half word transmission instructions are very useful for 
handling addresses, and they provide a convenient means of setting up an 
accumulator whose right half is to be used for indexing while a control count 
is kept in the left half. Eg this pair of instructions loads the 18-bit numbers 
M and N into the left and right halves respectively of an accumulator that is 
addressed symbolically as XR. 



HRLZI 
HRRI 



XK,M 
XR,7V 



Of course the source program must somewhere define the value of the 
symbol XR as an octal number between 1 and 17. 

Suppose that at some point we wish to use the two halves of XR inde- 
pendently as operands (taken as 1 8-bit positive numbers) for computations. 
We can begin by moving XR left to the right half of another accumulator 
AC and leaving the contents of XR right alone in XR. 



HLRZM 
HLLI 



XR,AC 
XR, 



;Clear XR left 



It is not necessary to clear the 
other half of XR when load- 
ing the first half word. But 
any instruction that modifies 
the other half is faster than 
the corresponding instruction 
that does not, as the latter 
must fetch the . destination 
word in order to save half of 
it. (The difference does not 
apply to self mode, for here 
the source and destination are 
the same.) 



2.2 FULL WORD DATA TRANSMISSION 

These are the instructions whose basic purpose is to move one or more full 
words of data from one place to another, usually from an accumulator to a 
memory location or vice versa. In a few cases instructions may perform 
minor arithmetic operations, such as forming the negative or the magnitude 
of the word being processed. 



EXCH 



Exchange 



2.90 (3.01) MS 



250 



. 89 12 13 14 17 18 

Move the contents of location E to AC and move AC to location E. 



3S 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) jus. 



2-10 

The time depends on the 
number and type of trans- 
fers. Assuming at least one 
word is moved a BLT takes 
.97 (1.08) Ais plus 2.26 (2.48) 
JUS per transfer from fast 
memory to core and 2.61 
(2.83) fjts per transfer from 
core to fast memory or from 
one core location to another. 



BLT 



28 

CENTRAL PROCESSOR 

Block Transfer 



§2.2 



251 


A 


I 


X 


Y \ 



89 



12 13 14 



17 18 



35 



Beginning at the location addressed by AC left, move words to another area 
of memory beginning at the location addressed by AC right. Continue until 
a word is moved to location £. The total number of words in the block is 
thus£:-ACR+ 1. 



Caution 

Priority interrupts are allowed during the execution of this instruction, 
following the processing of each word. If an interrupt occurs, the BLT 
stores the source and destination addresses for the next word in AC, so 
when, the processor restarts upon the return to the interrupted program, 
it actually resumes at the correct point within the BLT. Therefore, 
unless the interrupt system is inactive, A and X must not address the 
same register as this would produce a different effective address calcula- 
tion upon resumption should an interrupt occur; and the program must 
not attempt to load an accumulator addressed either by ^ or X unless it 
is the final location being loaded. Furthermore, the program cannot 
assume that AC is the same after the BLT as it was before. 



Examples. This pair of instructions loads the accumulators from memory 
locations 2000-20 17. 



HRLZI 
BLT 



17,2000 
17,17 



;Put 2000 000000 in AC 17 



But to transfer the block in the opposite direction requires that one accumu- 
lator first be made available to the BLT: 



MOVEM 17,2017 
MOVE! 17,2000 
BLT 17,2016 



;Move AC 17 to 2017 in memory 
;Move the number 2000 to AC 17 



If at the time the accumulators were loaded the program had placed in loca- 
tion 2017 the control word necessary for storing them back in the same 
block (2000), the three instructions above could be replaced by 



EXCH 
BLT 



17,2017 
17,2016 



Move Instructions 

Each of these instructions moves a single word, which may be changed in the 
process {eg its two halves may be swapped). There are four instructions, 



/' 



29 



§2.2 



FULL WORD DATA TRANSMISSION 



2-11 



each with four modes that determine the source and destination of the word 
moved. 



Mode 


Suffix 


Source 


Destination 


Basic 


* 


E 


AC 


Immediate 


I 


The word 0,£ 


AC 


Memory 


M 


AC 


E 


Self 


S 


E 


E, but also AC 
if ^ is nonzero 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) fis in memory 
mode, .20 (.09) jus in self 
mode. 

When E addresses a fast 
memory location, a move in- 
struction takes .34 /is less in 
basic mode, .46 (.35) fjs less 
in memory mode, .54 (.43) fjs 
less in self mode. 



MOVE 



Move 



200 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



Move one word from the source to the destination specified by M. 
source is unaffected, the original contents of the destination are lost. 



35 



The 



MOVE 


Move 


MOVE! 


Move Immediate 


MGVEM 


Move to Memory 


MOVES 


Move to Self 



200 


2.21 (2.43) MS 


201 


1.36 (1.47) MS 


202 


2.47 (2.58) MS 


203 


2.76 (2.87) MS 



MOVEI loads the word O.^" 
into AC and is thus equiva- 
lent to HRRZI. If A is zero, 
MOVES is a no-op; otherwise 
it is equivalent to MOVE. 



MOVS 



204 



Move Swapped 



M 



X 



67 89 



12 13 14 



17 18 



D 



35 



Interchange the left and right halves of the word from the source specified 
by M and move it to the specified destination. The source is unaffected, the 
original contents of the destination are lost. 



MOVS 


Move Swapped 


204 


2.21 (2,43) jus 


MOVSI 


Move Swapped Immediate 


205 


1.36(L47)ms 


MOVSM 


Move Swapped to Memory 


206 


2.47 (2.58) MS 


MOVSS 


Move Swapped to Self 


207 


2.76 (2.87) MS 



Swapping halves in immediate 
mode loads the word £",0 into 
AC. MOVSI is thus equivalent 
toHRLZI. 



MOVN 



Move Negative 



210 


M 


A 


I 


X 


Y 



67 89 



17 18 



35 



Negate the word from the source specified by M and move it to the specified 
destination. If the source word is fixed point -2^^ (400000 000000) set the 



MAY 1968 



2-12 



30 



CENTRAL PROCESSOR 



§2.2 



MOVNI loads AC with the 
negative of the word 0, E and 
can set no flags. 



Overflow and Carry 1 flags. (Negating the equivalent floating point -1 X 2*^'^ 
sets the flags, but this is not a normalized number.) If the source word is 
zero, set Carry and Carry 1. The source is unaffected, the original contents 
of the destination are lost. 



MOVN 


Move Negative 


210 


2.39 (2.61) MS 


MOVNI 


Move Negative Immediate 


211 


1.54 (1.65) MS 


MOVNM 


Move Negative to Memory 


212 


2.65 (2.76) MS 


MOVNS 


Move Negative to Self 


213 


2.94 (3.05) MS 



The word 0,E is equivalent 
to its magnitude, so MOVMI 
is equivalent to MOVEI. 



MOVM 



Move Magnitude 



2 14 


M 


A 


71 


X 


Y 



6 7 8 9 



12 13 14 



17 18 



35 



Take the magnitude of the word contained in the source specified by M and 
move it to the specified destination. If the source word is fixed point -2^^ 
(400000 000000) set the Overflow and Carry 1 flags. (Negating the equiva- 
lent floating point -1 X 2^^'' sets the flags, but this is not a normalized num- 
ber.) The source is unaffected, the original contents of the destination are 
lost. 



MOVM 


Move Magnitude 


214 


2.39 (2.61) MS 


MOVMI 


Move Magnitude Immediate 


215 


1.54 (1.65) MS 


MOVMM 


Move Magnitude to Memory 


216 


2.65 (2.76) MS 


MOVMS 


Move Magnitude to Self 


217 


2.94 (3.05) MS 



An example at the end of the preceding section demonstrates the use of a 
pair of immediaAe-mode half word transfers to load an address and a control 
count into an accumulator. The same result can be attained by a single move 
instruction. This saves time but still requires two locations. Eg if the num- 
ber 200 001400 is stored in location M, the instruction 

MOVE AC,M 

loads 200 into AC left and 1400 into AC right. If the same word, or its nega- 
tive, or with its halves swapped, must be loaded on several occasions, then 
both time and space can be saved as each transfer requires only a single move 
instruction that references M. 



Pushdown List 

These two instructions insert and remove full words in a pushdown list. T|ie 
address of the top item in the list is kept in the right half of a pointer in AC, 
and the program can keep a control count in the left half. There are also 



MAY 1968 



§2.2 



31 



FULL WORD DATA TRANSMISSION 



two subroutine-calling instructions that utilize a pushdown list of jump ad- 
dresses [§2.9] . 



2-13 



PUSH 



Push Down 



3.85 (4.07) MS 



261 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC to increment both halves by one, then move the con- 
tents of location E to the location now addressed by AC right. If the addi- 
tion causes the count in AC left to reach zero, set the Pushdown Overflow 
flag. The contents of E are unaffected, the original contents of the location 
added to the list are lost. 



Keeping instructions and the 
pushdown list in different 
memories saves .47 (.36) jus. 

When the word added to 
the list is from fast memory, 
PUSH takes .34 yi^ less than 
the time given. 



POP 



Pop Up 



3.93 (4.15) MS 



2 62 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Move the contents of the location addressed by AC right to location E, then 
subtract 1 00000 Ig from AC to decrement both halves, by one. If the sub- 
traction causes the count in AC left to reach -1, set the Pushdown Overflow 
flag. The original contents of E are lost. 

Because of the order in which the operands are stored, the instruction 
POP AC, AC would load the contents of the location addressed by AC right 
into AC on top of the pushdown count, destroying it. 



When the word taken from 
the list is placed in fast mem- 
ory, POP takes .46 (.35) ms 
less than the time given." 



The incrementing and decrementing of both halves of AC simultaneously 
is effected by adding and subtracting 1 00000 Ig. Hence a count of -2 in AC 
left is increased to zero if 2^^ - 1 is incremented in AC right, and conversely, 
1 in AC left is decreased to - 1 if zero is decremented in AC right. 

A pushdown list is simply a set of consecutive memory locations from 
which words are read in the order opposite that in which they are written. 
In more general terms, it is any 4ist in which the only item that can be re- 
moved at any given time is the last item in the list. This is usually referred 
to as "first in, last out" or "last in, first out". Supposb locations a, b, c, ... 
are set aside for a pushdown list. We can deposit data in a, b, c, d, then read 
d, then write in d and e, then read e, d, c, etc. 

Note that by using the Pushdown Overflow flag and a control count in AC 
left, the programmer can set a limit to the size of the list by starting the 
count negative, or he can prevent the program from extracting more words 
than there are in the list by starting the count at zero, but he cannot do both 
at once. 



32 

2-14 CENTRAL PROCESSOR §2.2 

Pushdown storage is very convenient for a program that can use data 
stored in this manner as the pointer is initialized only once and only one 
accumulator is required for the most complex pushdown operations. To ini- 
tialize a pointer P for a list to be kept in a block of memory beginning at 
BLIST and to contain at most A^ items, the following suffices. 

MOVSI ?~N 
HRRI P,BUST-1 

Of course the programmer must define BLIST elsewhere and set aside loca- 
tions BLIST to BLIST + TV - 1 . Using Macro to full advantage one could 
instead give 

MOVE P,[IOWD A^,BLIST] 

where the pseudoinstruction 

lOWD J,K 

is replaced by a word containing -J in the left half and ^ - 1 in the right. 
Elsewhere there would appear 

BLIST: BLOCK A^ 

which defines BLIST as the current contents of the location counter and sets 
aside the A'^ locations beginning at that point. 

In the PDP-10 the pushdown list is kept in a random access core mem- 
ory, so the restrictions on order of entry and removal of items actually apply 
only to the standard addressing by the pointer ^in pushdown instructions - 
other addressing methods can reference any item at any time. The most 
convenient way to do this is to use the right half of the pointer as an index 
register. To move the last entry to accumulator AC we need simply give 

MOVE AC,(P) 

Of course this does not shorten the list - the word moved remains the last 
item in it. 

One usually regards an index register as supplying an additive factor for a 
basic address contained in an instruction word, but the index register can 
supply the basic address and the instruction the additive factor. Thus we can 
retrieve the next to last item by giving 

MOVE AC,-1(P) 
and so forth. Similarly 

PUSH * P,-3(P) 
adds the third to last item to the end of the list; 

POP P,-2(P) 

removes the last item and inserts it in place of the next to last item in the 
shortened Hst. 



• 33 _ , 

§2.3 BYTE MANIPULATION - 2-15 

2.3 BYTE MANIPyLATION 

This set of five instructions allows the programmer to pack or unpack bytes 
of any length anywhere within a word. Movement of a byte is always 
between AC and a memory location: a deposit instruction takes a byte from 
the right end of AC and inserts it at any desired positioin in the memory 
location; a load instruction takes a byte from any position in the memory 
location and places it right-justified in AC. 

The byte manipulation instructions have the standard memory reference 
format, but the effective address E is used to retrieve a pointer, which is used 
in turn to locate the byte or the place that will receive it. The pointer has 
the format 



P S IX Y 



56 11 12 13 14 17 18 35 

where S is the size of the byte as a number of bits, and P is its position as the 
number of bits remaining at the right of the byte in the word (eg if P is 3 the 
rightmost bit of the byte is bit 32 of the word). The rest of the pointer is 
interpreted in the same way as in an instruction: /, X and Y are used to cal- 
culate the address of the location that is the source or destination of the 
byte. Thus the pointer aims at a word whose format is 



^^BITS^^ P BITS 



3S-P-5+t 35-P ZS-Pf\ 35 

where the shaded area is the byte. 

To facilitate processing a series of bytes, several of the byte instructions 
increment the pointer, ie modify it so that it points to the next byte position 
in a set of memory locations. Bytes are processed from left to right in a 
word, so incrementing merely replaces the current value of /* by P - 5, unless 
there is insufficient space in the present location for another byte of the 
specified size (i* -5 < 0). In this case Y is increased by one to point to the 
next consecutive location, and P is set to 36 —5" to point to the first byte at 
the left in the new location. 

Caution 

Do not allow Y to reach maximum value. The whole pointer is incre- 
mented, so if Y is 2*^- 1 it becomes zero and X is also incremented. 
• The address calculation for the pointer uses the original X, but if a pri- 
ority interrupt should occur before the calculation is complete, the in- 
cremented X is used when the instruction is repeated. 

Among these five instructions on^ simply increments the pointer, the 
others load or deposit a byte with or without incrementing. Brackets 
enclose the additional time required when incrementing overflows the word 
boundary. 



2-16 

Keeping the pointer in fast 
memory saves .34 /is. Taking 
bytes from a fast memory 
location saves another .34 jus. 



LDB 



34 

CENTRAL PROCESSOR 

Load Byte 



§2.3 
4.02(4.35)-f .15(P + 5) [+.26] ms 



135 


A 


I 


X 


Y 



12 13 14 



17 18 



Retrieve a byte of S bits from the location and position specified by the 
pointer contained in location E, load it into the right end of AC, and clear 
the remaining AC bits. The location containing the byte is unaffected, the 
original contents of AC are lost. 



Keeping the pointer in fast 
memory saves .34 jus. Keeping 
instructions and the packing 
area in different memories 
saves .20 (.09) (i&. Packing 
bytes in fast memory saves 
.54 (.43) MS. 



DPS 



Deposit Byte 



4.87(5.20) + .15(i> + 5) [+.26] ms 



137 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Deposit the right S bits of AC into the location and position specified by the 
pointer contained in location E. The original contents of the bits that receive 
the byte are losi, AC and the remaining bits of the deposit location are 
unaffected. 



Keeping the pointer in fast 
memory saves .54 (.43) ms; 
keeping it in a different mem- 
ory from the instruction saves 
^.20 (.09) MS 

The A portion of this instruc- 
tion is ignored. 



IBP 



Increment Byte Pointer 



2.87(2.98) [+.26] ms 



13 3 


A 


I 


X 


Y 



89 



12 13 14 



1718 



35 



Increment the byte pointer in location E as explained above. 



Keeping the pointer in fast 
memory saves .34 ms. Taking 
bytes from a fast memory 
location saves another .34 ms. 



ILDB 



Increment Pointer and Load Byte 



4.24 (4.57) + . 15(F + S) [+.26] ms 



134 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



3S 



Increment the byte pointer in location E as explained above. Then retrieve a 
byte of S bits from the location and position specified by the newly incre- 
mented pointer, load it into the right end of AC, and clear the remaining AC 
bits. The location containing the byte is unaffected, the original contents of 
AC are lost. 



Keeping the pointer in fast 
memory saves .34 ms. Keeping 
instructions and the packing 
area in different memories 
saves .20 (.09) ms. Packing 
bytes in fast memory saves 
.54 (.43) MS. 



IDPB Increment Pointer and Deposit Byte 

5,29(5.51) + .i5(P + *S') [ + .26] MS 



136 



89 121314 1718 35 

Increment the byte pointer in location E as explained above. Then deposit 



35 



§2.4 



LOGIC 



the right 5 bits of AC into the location and position specified by the newly 
incremented pointer. The original contents of th£ bits that receive the byte 
are lost, AC and the remaining bits of the deposit location are unaffected. 



Note that in the pair of instructions that both increment the pointer and 
process a byte, it is the modified pointer that determines the byte location 
and position. Hence to unpack bytes from a block of memory, the program 
should set up the pointer to point to a byte just before the first desired, and 
then load them with a loop containing an ILDB. If the first byte is at the 
left end of a word, this is most easily done by initializing the pointer with a 
P of 36 (448). Incrementing then replaces the 36 with 36 -S to point to the 
first byte. At any time that the program might inspect the pointer during 
execution of a series of ILDBs or IDPBs, it points to the last byte processed 
(this may not be true when the pointer is tested from an interrupt routine 
[§2.13]). 

Special Considerations. If S is greater than P and also greater than 36, 
incrementing produces a new P equal to 100-5 rather than 36-5". For 
S>36 the byte is at most the entire word; for P>36 no byte is processed 
(loading merely clears AC). If both P and S are less than 36 but P-\-S> 36, 
a byte of size 36 - Z' is loaded from position P, or the right 36 -P bits of the 
byte are deposited in position P, 



2.4 LOGIC 



2-17 



For logical operations the PDF- 10 has instructions for shifting and rotating 
as well as for performir^g the complete set of sixteen Boolean functions of 
two variables (including those in which the result depends on only one or 
neither variable). The Boolean functions operate bitwise on full words, so 
each instruction actually performs thirty-six logical operations simultane- 
ously. Thus in the and function of two words, each bit of the result is the 
AND of the corresponding bits of the operands. The table on page 2-23 lists 
the bit configurations that result from the various operand configurations for 
all instructions. 

Each Boolean instruction has four modes that determine the source of the 
non-AC operand, if aay, and the destination of the result. 



Mode 


Suffix 


Source of non- 
AC operand 


Destination 
of result 


Basic 

Immediate 
Memory 
Both 


I 

M 
B 


E 

The word 0, E 

E 

E 


AC 

AC 

E 

AC and E 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) jlis in memory 
and both modes in the first 
four of these instructions 
(those that have no operand 
or only an AC operand), .20 
(.09) MS in memory and both 
modes in the remaining 
twelve (those that have a 
memory or immediate op- 
erand). 



36 



2-18 

A Boolean instruction in 
which E addresses a fast 
memory location takes .46 
(.35) MS less in memory or 
both mode if it has no oper- 
and or only an AC operand. 
If it has a memory operand, 
it takes .34 ms less in basic 
mode, .54 (.43) ^ less in 
memory or both mode. 



CENTRAL PROCESSOR 



§2.4 



For an instruction without an operand (one that merely clears a location or 
sets it to all Is) the modes differ only in the destination of the result, so 
basic and immediate modes are equivalent. The same is true also of an 
instruction that uses only an AC operand. When specified by the mode, the 
result goes to the accumulator addressed by A , even when there is no AC 
operand. 



SETZ and SETZI are equiva- 
lent (both merely clear AC). 
Macro also recognizes 
CLEAR, CLEARI, CLEARM 
dnd CLEARB as equivalent to 
the set-to-zeros mnemonics. 



SETZ 



400 



Set to Zeros 



M 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to all Os. 

SETZ Set to Zeros 400 1.36 (1.47) ms 

SETZI Set to Zeros Immediate 401 1.36 ( 1.47) ms 

SETZM ^ Set to Zeros Memory 402 2.33 (2.44) ms 

SETZB Set to Zeros Both 403 2.33 (2.44) ms 



SETO and SETOI are equiva- 
lent. 



SETO 



Set to Ones 



474 


M 


A I 


X 


Y 


6 

Change the cor 

SETO Se 
SETOI Se 
SETOM Se 
SETOB Se 


7 8 

tteni 

tto 
tto 
tto 
tto 


9 12 13 

s of the de 

Ones 

Ones Imm 
Ones Mem 
Ones Both 


14 17 

stination 

ediate 
ory 


18 

specified by M tc 

474 
475 
476 

477 


.all 1 


35 

S. 

1.36 (1.47) MS 
1.36 (1.47) MS 
2.33 (2.44) MS 
2.33 (2.44) MS 



SETA 



Set to AC 



SETA and SETAI are no-ops. 
SET AM and SETAB are both 
equivalent to MOVEM (all 
move AC to location E). 



424 



M 



67 89 



12 13 14 



17 18 



35 



Make the contents of the destination specified by M equal to AC. 

SETA Set to AC 424 1.50 (1,61) ms 

SETAI Set to AC Immediate 425 1.50 (1.61) ms 

SETAM Set to AC Memory 426 2.47 (2.58) ms 

SETAB Set to AC Both 427 2.47 (2.58) ms 



§2.4 
SETCA 



37 



LOGIC 



Set to Complement of AC 



450 


M 


A 


I 


X 


y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the complement of 
AC. 



SETCA Set to Complement of AC 

SETCAI Set to Complement of AC Immediate 

SETCAM Set to Complement of AC Memory 

SETCAB Set to Complement of AC Both 



450 
1,50(1.61)ms 

451 
1.50 (1.61) MS 

452 
2.47 (2.58) MS 

453 
2.47 (2.58) jus 



2-19 



SETCA and SETCAI are 
equivalent (both complement 
AC). 



SETM 



Set to Memory 



414 M A I X 




Y 




6 7 89 12 13 14 17 18 






35 


Make the contents of the destination specified by M equal 


to the specified 


operand. 








SETM . Set to Memory 


414 




2.21 (2.43) MS 


SETMI Set to Memory Immediate 


415 




1.36 (1.47) MS 


SETMM Set to Memory Memory 


416 




2.76 (2.87) MS 


SETMB Set to Memory Both 


417 




2.76 (2.87) MS 



SETM and SETMB are equiv- 
alent to MOVE. SETMI 
moves the word 0,E to AC 
and is thus equivalent to 
MOVEI. SETMM is a no-op 
that references memory. 



SETCM 



Set to Complement of Memory 



460 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the complement of 
the specified operand. 

SETCM Set to Complement of Memory 



SETGMI Set to Complement of Memory Immediate 



460 

2.21 (2.43) MS 

461 

1.36 (1.47) MS 
SETCMM Set to Complement of Memory Memory 462 

2.76 (2.87) MS 

SETCMB Set to Complement of Memory Both 463 

2.76 (2.87) MS 



SETCMI moves the comple- 
ment of the word 0,£' to AC. 
SETCMM complements loca- 
tion £". 



38 



2-20 



AND 



CENTRAL PROCESSOR 

And with AC 



§2.4 



404 



M 



X 



67 89 



17 18 



35 



Change the contents of the destination specified by M to the and function of 
the specified operand and AC. 

AND And 

AND I And Immediate 

ANDM And to Memory 

ANDB And to Both 



404 


2.35 (2.57) MS 


405 


1.50(1.61)MS 


406 


2.90 (3.01) MS 


407 


2.90 (3.01) MS 



ANDCA 



410 



And with Complement of AC 



M 



67' 89 



12 13 14 



Change the contents of the destination specified by M to the and function of 
the specified operand and the complement of AC. 



AN D CA And with Complement of AC 

AN DCAl And with Complement of AC Immediate 

ANDCAM And with Complement of AC to Memory 

ANDCAB And with Complement of AC to Both 



410 
2.70 (2.92) MS 

411 
1.85 (1.96) MS 

412 
3.52 (3.63) MS 

413 
3.52 (3.63) MS 



ANDCM And Complement of Memory with AC 



420 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the and function of 
the complement of .the specified operand and AC. 



ANOCM 
ANDCMI 



And Complement of Memory 

And Complement of Memory Immediate 



420 
2.35 (2.57) MS 
421 
1.50(1.61)ms 
ANDCMM And Complement of Memory to Memory 422 

2.90 (3.01) M^ 
ANDCMB And Complement of Memory to Both 423 

2.90 (3.01) MS 

















39 




§2.4 




LOGIC 




ANDCB 


And Complements of Both 






440 


M 


A 


I 


X 




Y 


1 





67 89. 12 


13 14 17 18 




3S 



Change the contents of the destination specified by M to the and function of 
the complements of both the specified operand and AC. The result is the 
NOR function of the operands. 

And Complements of Both 



ANDCB 

ANDCBI And Complements of Both Immediate 

AN D CBM And Complements of Both to Memory 

ANDCBB And Complements of Both to Both 



440 
2.70 (2.92) iixs 

441 
1.85 (1.96) MS 

442 
3.52 (3.63) MS 

443 
3.52 (3.63) MS 



2-21 



lOR 



Inclusive Or with AC 



434 


M 


A 


I 


X 


! 



67 89 



n 13 14 



1718 



35 



Change the contents of the destination specified by M to the inclusive or 
function of the specified operand and AC. 

10 R Inclusive Or 

1 R I Inclusive Or Immediate 

10 RM Inclusive Or to Memory 

10 RB Inclusive Or to Both 



434 


2.35 (2.57) MS 


435 


1.50 (1.61) MS 


436 


2.90 (3.01) MS 


437 


2.90 (3.01) MS 



Macro also recognizes OR, 
ORI, ORM and ORB as equiv- 
alent to the inclusive or mne- 
monics. 



ORCA 



Inclusive Or with Complement of AC 



454 



M 



6 7 8 9 



12 13 14 



17 18 



ORCA 



Or with Complement of AC 



Change the contents of the destination specified by M to the inclusive or 
function of the specified operand and the complement of AC. 

454 
2.70 (2.92) MS 

ORCAI Or with Complement of AC Immediate 455 

1.85 (1.96) MS 

OR CAM Or with Complement of AC to Memory 456 

3.52 (3.63) MS 

OR CAB Or with Complement of AC to Both 457 

3.52 (3.63) MS 



ORCM 



40 

CENTRAL PROCESSOR 

Inclusive Or Complement of Memory with AC 



!.4 



464 



M 



67 89 



12 13 14 



1718 



35 



Change the contents of the destination specified by M to the inclusive or 
function of the complement of the specified operand and AC. 

464 

235 (2.57) JUS 

465 

1-50(1.61) JUS 

Or Complement of Memory to Memory 



ORCM 
ORCMI 
ORCMM 
ORCMB 



Or Complement of Memory 

Or Complement of Memory Immediate 



ORCB 



Or Complement of Memory to Both 
Inclusive Or Complements of Both 



466 
2.90 (3.01) MS 

467 
2.90 (3.01) MS 



470 



M 



67 89 



12 13 14 



17 18 



J 



35 



Change the contents of the destination specified by M to the inclusive or 
function of the complements of both the specified operand and AC. The 
result is the nand function of the operands. 



ORCB Or Complements of Both 

ORCBI Or Coniplements of Both Immediate 

R CBM Or Complements of Both to Memory 

ORCBB Or Complements of Both to Both 



470 
2.70 (2.92) |us 

471 
1,85(1.96) MS 

472 
3.52 (3.63) MS 

473 
3.52 (3.63) MS 



XOR 



Exclusive Or with AC 



430 



M 



67 89 



12 13 14 



17 18 



35 



Change the contents of the destination specified by M to the exclusive or 
function of the specified operand and AC, 

Exclusive Or 430 2.35 (2.57) ms 

Exclusive Or Immediate 431 1.50 (1.61) ms 

Exclusive Or to Memory 432 2.90 (3.01) ms 

Exclusive Or to Both 433 2.90 (3,01) ms 



XOR 
XORI 
XORM 
XORB 



The original contents of the destination can be recovered except in XORB, 
where both operands are replaced by the result. In the other three modes 
the replaced operand is restored by repeating the instruction in the same 
mode, ie by taking the exclusive or of the remaining operand and the result. 



41 

§2.4 toGic 

EQV Equivalence with AC 



2-23 



444 



M 



X 



D 



6 7 89 12 13 14 17 18 35 

Change the contents of the destination specified by A/ to the complement of 
the exclusive or function of the specified operand and AC (the result has Is 
wherever the corresponding bits of the operands are the same), 

EQV Equivalence 444 235 (2.57) /xs 

EQVI Equivalence Immediate 445 1.50 (1.61) /is 

EQVM Equivalence to Memory 446 2.90 (3.01) /is 

EQVB Equivalence to Both 447 2.90 (3.01) ms 

The original contents of the destination can be recovered except in EQVB, 
where both operands are replaced by the result. In the other three modes 
the replaced operand is restored by repeating the instruction in the same 
mode, ie by taking the equivalence function of the remaining operand and 
the result. 



For the four possible bit configurations of the two operands, the above 
sixteen instructions produce the following results. In each case the result as 
listed is equal to bits 3-6 of the instruction word. 





AC 





1 







Mode Specified Operand 








1 




SETZ 
















AND 















ANDCA 














SETM 














ANDCM 







.1 







SETA 







1 






XOR 







1 






lOR 







i 






ANDCB 













EQV 













SETCA 













ORCA 













SETCM 






1 







ORCM 






1 







ORCB 






1 







SETO 






1 







2-24 



42 



CENTRAL PROCESSOR 



§2.4 



LSH 



Shift and Rotate 

The remaining logical instructions shift or rotate right or left the contents of 
AC or the contents of two accumulators, A and ^ + 1 (mod 203), concat- 
enated into a 72-bit register with A on the left. The illustration below 
shows the movement of information these instructions produce in the accu- 








4 


« 










35 



LSHi 



>^ + 1 



35 



35 



ROT 











^ 




* 


* 










3 35 





ROTC 















>? 




/I +1 














35 




35 





ASH 



/i 




^ 














1 35 





ASHC 



u 



,/^+T 



^ + 1 



35 . 1 



35 



ACCUMULATOR BIT FLOW IN SHIFT AND ROTATE INSTRUCTIONS 



43 



§2.4 



LOGIC 



2-25 



mulators. In a (logical) shift the contents of a register are moved bit-to-bit 
with Os brought in at the end being vacated; information shifted out at the 
other end is lost. [For a discussion of arithmetic shifting see §2.5.] In 
rotation the contents are moved cyclically such that information rotated oiit 
at one end is put in at the other. 

The number of places moved is specified by the result of the effective 
address calculation taken as a signed number (in twos complement notation) 
modulo 2^ in magnitude. In other words the effective shift E is the number 
composed of bit 18 (which is the sign) and bits 28-35 of the calculation 
result. Hence the programmer may specify the shift directly in the instruc- 
tion (perhaps indexed) or give an indirect address to be used in calculating 
the shift. A positive E produces motion to the left, a negative E to the right; 
maximum movement is 255 places. 



LSM 



Logical Shift 



Left: 
Right: 



1.62(1.73) + 
1.46(1.57) + 



15|£'Ims 
151^1 MS 



242 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Shift AC the number of places specified hy E. If E is positive, shift left 
bringing Os into bit 35; data shifted out of bit is lost. If £" is negative, shift 
right bringing Os into bit 0; data shifted out of bit 35 is lost. 



LSHC 



Logical Shift Combined 



Left: 2.00(2.11) + .15|£|ius 
Right: 1.84(1.95) + .15|£iMS 



246 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Concatenate accumulators A and ^ + 1 with A on the left, and shift the 
7^-bit combination the number of places specified by E. If E is positive, 
shift left bringing Os into bit 71 (bit 35 of AC ^ + 1); bit 36 is shifted into bit 
35 ; data shifted out of bit is lost. If E is negative, shift right bringing Os 
into bit 0; bit 35 is shifted into bit 36; data shifted out of bit 71 is lost. 



ROT 



Rotate 



Left: 1.62 (1.73) + .15|£'| MS 
Right: 1.46 (1.57) +.15|£'jpts 



24 1 ^ 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Rotate AC the number of places specified by E. ME is positive, rotate left; 
bit is rotated into bit 35. HE is negative, rotate right; bit 35 is rotated 
into bit 0. 



2-26 



ROTC 



44 

CENTRAL PROCESSOR 

Rotate Combined 



§2.5 

Left: 2.00(2.11) + .15|£'iMs 
Right: 1.84(1.95) + .15|£|ms 



245 


A 


I 


X Y 



89 



12 13 14 



17 18 



Concatenate accumulators A and ^ + 1 with A on the left, and rotate the 
72-bit combination the number of places specified by E. If E is positive, 
rotate left; bit is rotated into bit 71 (bit 35 of AC ^ + 1) and bit 36 into bit 
35. If E is negative, rotate right; bit 35 is rotated into bit 36 and bit 71 into 
bitO. 



2.5 FIXED POINT ARITHMETIC 



Overflow is determined di- 
rectly from the carries, not 
from the carry flags, as their 
states may reflect events in 
previous instructions. 



For fixed point arithmetic the PDP-10 has instructions for arithmetic shift- 
ing (which is essentially multiplication by a power of 2) as well as for per- 
forming addition, subtraction, multiplication and division of numbers in 
fixed point format [§1.1]. In such numbers the position of the binary point 
is arbitrary (the programmer may adopt any point convention). The add and 
subtract instructions involve only single length numbers, whereas multiply 
supplies a double length product, and divide uses a double length dividend. 
The high and low order words respectively of a double length fixed point 
number are in accumulators A and A-\-\ (mod 208), where the magnitude is 
the 70-bit string in bits 1-35 of the two words and the signs of the two are 
identical. There are also integer multiply and divide instructions that involve 
only single length numbers and are especially suited for handling smaller 
integers, particularly those of eighteen bits pr less such as addresses (of 
course they can be used for small fractions as well provided the programmer 
keeps track of the binary point). For convenience in the following, all oper- 
ands are assumed to be integers (binary point at the right). 

The processor has four flags, Overflow, Carry 0, Carry 1 and No Divide, 
that indicate when the magnitude of a number is or would be larger than can 
be accommodated. Carry and Carry 1 actually detect carries out of bits 
and 1 in certain instructions that employ fixed point arithmetic operations; 
the add and subtract instructions treated here, the move instructions that 
produce the negative or magnitude of the word moved [§2.2], and the 
arithmetic test instructions that increment or decrement the test word 
[ §2.7] . In these instructions an incorrect result is indicated - and the Over- 
flow flag set - if the carries are different, ie if there is a carry into the sign 
but not out of it, or vice versa. The Overflow flag is also set by No Divide 
being set, which means the processor has failed to perform a division because 
the magnitude of the dividend is greater than or equal to thac of the divisor, 
or in integer divide, simply that the divisor is zero. In other overflow cases 
only Overflow itself is set: these include too large a product in multiplica- 
tion, and loss of significant bits in left arithmetic shifting. 

These flags can be read and controlled by certain program control instruc- 
tions [ §2.9] , and Overflow is available as a processor condition (via in-out 



§2.5 



45 



FIXED POINT ARITHMETIC 



2-27 



instructions [§2.14]) that can request a priority interrupt if enabled. The 
conditions detected can only set the flags and the hardware does not clear 
them, so the program must clear them before an instruction if they are to 
give meaningful information about the instruction afterward. However, the 
program can check the flags following a series of instructions to determine 
whether the entire series was free of the types of error detected. 

All but the shift instructions have four modes that determine the source 
of the non-AC operand and the destination of the result. 



Besides indicating error types, 
the carry flags facilitate per- 
forming multiple precision 
arithmetic. 







Source of non- 


Destination 


Mode 


Suffix 


A C operand 


of result 


Basic 




E 


AC 


Immediate 


I 


The word 0,^ 


AC 


Memory 


M 


E 


E 


Both 


B 


E 


AC and E 



ADD 



Add 



270 


M 


. A 


I 


X 


Y 



67 89 



12 13 14 



35 



Add the operand specified by M to AC and place the result in the specified 
destination. If the sum is > 2^^ set Overflow and Carry 1 ; the result stored 
has a minus sign but a magnitude in positive form equal to the sum less 2^^. 
If the sum is < -2^^ set Overflow and Carry 0; the result stored has a plus 
sign but a magnitude in negative form equal to the sum plus 2^^. Set both 
carry flags if both summands are negative, or their signs differ and their mag- 
nitudes are equal or the positive one is the greater in magnitude. 



ADD 


Add 


ADDI 


Add Immediate 


AODM 


Add to Memory 


ADDB 


Add to Both 



270 


2.53 (2.75) MS 


271 


1.68 (1.79) MS 


272 


'3.08 (3.19) MS 


273 


3.08 (3.19) MS 



SUB 



Subtract 



274 


M 


A 


I 


X 


Y 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) ms in ADDM 
and ADDB. 

When E addresses a fast 
memory location, ADD takes 
.34 MS less than the time 
given, ADDM and ADDB take 
.54 (.43) MS less. 



12 13 14 



17 18 



Subtract the operand specified by M from AC and place the result in the 
specified destination. If the difference is > 2^^ set Overflow and Carry 1 ; 
the result stored has a minus sign but a magnitude in positive form equal to 
the difference less 2^^. If the difference is < -2^^ set Overflow and Carry 0; 
the result stored has a plus sign but a magnitude in negative form equal to 
the difference plus 2^^. Set both carry flags if the signs of the operands are 
the same and AC is the greater or the two are equal, or the signs of the 
operands differ and AC is negative. 



MAY 1968 



46 



:-:8 



CENTRAL PROCESSOR 



§2.5 



Keeping instructions and op- 
erands in different memories 
saves .20 (.09) ^s in SUBM 
and SUBB. 

Wlien E addresses a fast 
memory location. SUB takes 
.34 jjis less than the time 
given. SUBM and SUBB take 
.54 (.43) Ais less. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /ks in MULM. 
.31 (.20)MSinMULB. 

Wlien E addresses a fast 
memory location. MUL takes 
.34 fjLs less than the time 
given. MULM takes .80 (.69) 
ps less, and MULB takes .64 
(.53)^5 less. 



SUB 


Subtract 


SUBI 


Subtract Immediate 


SUBM 


Subtract to Memory 


SUBB 


Subtract to Both 



274 


2.53 (2.75) JUS 


275 


1.68 (1.79) MS 


276 


3.08 (3.19) MS 


277 


3.08 (3.19) MS 



MUL 



Multiply 



24 



M 



12 13 14 



17 1! 



Multiply AC by the operand specified by M, and place the high order word 
of the double length result in the specified destination. UM specifies AC as 
a destination, place the low order word in accumulator A + \. If both oper- 
ands are -2^^ set Overflow: the double length result stored is -2"^*^. 



MUL 


Multiply 


MULI 


Multiply Immediate 


MULM 


Multiply to Memory 


MULB 


Multiply to Both 



224 


10.60 (10.82) MS 


225 


8.58 (8.69) MS 


226 


11.41 (11.63) MS 


227 


11.41 (11.63) MS 



Timing. The times given above are average. The algorithm modifies the 
nmning sum of partial products at each 1-0 or 0-1 transition scanning from 
one bit to the next in the multiplier, which is the operand specified by the 
mode; in other words the number of operations equals the number of pairs 
of adjacent bits that differ in the multiplier mcluding the sign bit and taking 
the bit at the right of the LSB as (an LSB of 1 is regarded as a transition). 
Minimum times with a zero multiplier are 



MUL 
MULI 
MULM 
MULB 



8.26 (8.48) MS 
7.41 (7.52) MS 
9.07 (9.29) MS 
9.07 (9.29) MS 



Tl^ese must be increased by . 1 3 ms for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



IMUL 



220 



Integer Multiply 



M 



6 7 8 9 



12 13 14 



17 18 



35 



Multiply AC by the operand specified by M, and place the sign and the 35 
low order magnitude bits of the product in the specified destination. Set 
Overflow if the product is > 2^^ or < -2^^ (ie if the high order word of the 
double length product is not null); the high order word is lost. 



§2.5 



47 

FIXER POINT ARITHMETIC 



2-29 



IMUL 


Integer Multiply 


220 


9.59 (9.81) MS 


tlVtULt 


Integer Multiply Immediate 


221 


8.09 (8.20) JUS 


IMULM 


Integer Multiply to Memory 


222 


10.56 (10.78) MS 


IMULB 


Integer Multiplx to Both 


223 


10.56 (10.78) MS 



Timing. The times given above are average. Refer' to the description of 
MUL for the timing effects of the multiplication algorithm. Minimum times 
with a zero multiplier are 



IMUL 


8.42 (8.64) MS 


IMULI 


7.57 (7.68) MS 


IMULM 


9.39 (9.61) MS 


IMULB 


9.39 (9.61) MS 



These must be increased by . 1 3 ms for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) ms in IMULM 
and IMULB. 

When E addresses a fast 
memory location, IMUL 
takes .34 ms less than the time 
given, IMULM and IMULB 
take .80 (.69) ms less. 



DiV 



Divide 



234 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



If the magnitude of the number in AC is greater than or equal to that of the 
operand specified by M, set Overflow and No Divide, and go immediately to 
the next instruction without affecting the original AC or memory operand in 
any way. Otherwise divide the double length number contained in accumula- 
tors A and ^ + 1 by the specified operand, calculating a quotient of 35 
magnitude bits including leading zeros. Place the unrounded quotient in the 
specified destination. If Af specifies AC as a destination, place the remainder, 
with the same sign as the dividend, in accumulator A+ 1 . 



DIV 


Divide 


DIVI 


Divide Immediate 


Diyivi 


Divide to Memory 


DIVB 


Divide to Both 



234 


16.2 (16.4) MS 


235 


15.4 (15.5) MS 


236 


17.1 (17.3) MS 


237 


17.1 (17.3) MS 



IDIV 



Integer Divide 



230 



M 



ZA 



67 89 



12 13 14 



[7 18 



35 



If the operand specified by M is zero, set Overflow and No Divide, and go 
immediately to the next instruction without affecting the original AC or 
memory operand in any way. Otherwise divide AC by the specified operand, 
calculating a quotient of 35 magnitude bits including leading zeros. Place 



Keeping instructions and op- 
erands in different memories 
saves .5 (.4) ms in DIVM, .3 
(.2) MS in DIVB. 

When E addresses a fast 
memory location, DIV takes 
.3 /Lts less than the time given, 
DIVM takes .8 (.7) ms less, 
and DIVB takes .6 (.5) ms 
less. 

If the division is not per- 
formed, only 2.5-3 ms are 
required. 



2-30 



48 

CENTRAL PROCESSOR 



§2,5 



Keeping instructions and op- 
erands in different memories 
saves .5 (.4) ^s in IDIVM, .3 
(.2)MsinlDIVB. 

When E addresses a fast 
memory location, IDIV takes 
.3 fis less than the time given, 
IDIVM takes .8 (.7) ^s less, 
and IDIVB takes .6 (.5) /us 
less. 

If the division is not per- 
formed, only 3-3.5 ^s are 
required. 



the unrounded quotient in the specified destination. If jW specifies AC as the 
destination, place the remainder, with the same sign as the dividend, in 
accumulator A + \. 



IDIV 


Integer Divide 


230 


16.5 (16.7) jLis 


IDIV! 


Integer Divide Immediate 


231 


15.7 (15.8) Ats 


IDIVM 


Integer Divide to Memory 


232 


17.4 (17.6) MS 


IDIVB 


Integer Divide to Both 


233 


17.4 (17.6) MS 



Example. The integer multiply and divide instructions are very useful for 
computations on addresses or character codes, or performing any integral 
operations in which the result is small enough to be accommodated in a 
single register. 

As an example suppose we wish to determine the parity of the 8-bit char- 
acter abcdefgh, where the letters represent the bits of the character. Ass\^- 
ing the character is right-justified in AC, we first duplicate it twice to the left 
producing 

abc def gha bed efg hab cde fgh 

where the bits (in positions 12^35) are grouped corresponding to the octal 
digits in the word. Anding this with 

001 001 001 001 Odl 001 001 001 

retains only the least significant bit in each 3-bit set, so we can represent the 
result by 

cfadgbeh 

where each letter represents an octal digit having the same value (0 or 1) as 
the bit originally represented by the same letter. Multiplying this by 
llllllllg generates the following partial products: 

















c 


f 


a 


d 


g 


b 


e 














c 


f 


a 


d 


g 


b 


e 


h 












c 


f 


a 


d 


g 


b 


e 


h 












c 


f 


a 


d 


g 


b 


e 


h 












c 


f 


a 


d 


g 


b 


e 


h 












c 


f 


a 


d 


g 


b 


e , 


h 












c 


f 


a 


d 


8 


b 


e 


h 












c 


f 


a 


d 


g 


b 


e 


h 












- 



Since any digit is at most 1, there can be no carry out of any column with 
fewer than eight digits unless there is a carry into it. Hence the octal digit 
produced by summing the center column (the one containing all the bits of 
the character) is even or odd as the sum of the bits is even or odd. Thus its 
least significant bit (bit 14 of the low order word in the product) is the par- 
ity of the character, if even, 1 if odd. 

The above may seem a very complicated procedure to do something 
trivial, but it is effected by this quite simple sequence (with the character 



§2.5 



49 



FIXED POINT ARITHMETIC 



2-31 



right-justified in AC): 



ONES: 



IMULI AC,200401 
AND ACONES 
IMUL AC, ONES 



1111111 



where the parity is indicated by AC bit 14. Of course, following the IMUL 
would be a test instruction to check the value of the bit. 



Arithmetic Shifting 

These two instructions produce an arithmetic shift right or left of the num- 
ber in AC or the double length number in accumulators A and A + l. Shifting 
is the movement of the contents of a register bit-to-bit. The operation dis- 
cussed here is similar to logical shifting [see §2.4 and the illustration on 
page 2-24] , but in an arithmetic shift only the magnitude part is shifted - 
the sign is unaffected. In a double length number the 70-bit string made up 
of the magnitude parts of the two words is shifted, but the sign of the low 
order word is made equal to the sign of the high order word. 

Null bits are brought in at the end being vacated: a left shift brings in Os at 
the right, whereas a right shift brings in the equivalent of the sign bit at thfe 
left. In either case, infomiation shifted out at the other end is lost. A smgle 
shift left is equivalent to multiplying the number by 2 (provided no bit of 
significance is shifted out); a shift right divides the number by 2. 

The number of places shifted is specified by the result of the effective 
address calculation taken as a signed number (in twos complement notation) 
modulo 2^ in magnitude. In other words the effective shift E is the number 
composed of bit 18 (which is the sign) and bits 28-35 of the calculation 
result. Hence the programmer may specify the shift directly in the instruc- 
tion (perhaps indexed) or give an indirect address to be used m calculating 
the shift. A positive E produces motion to the left, a negative E to the right; 
E is thus the power of 2 by which the number is multiplied. Maximum 
movement is 255 places. 



ASH 



Arithmetic Shift 



Left: 1,62(1.73) -S-.ISIE'I MS 
Right: l>t6(1.57) + .15|£'lMS 



1 240 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Shift AC arithmetically the number of places specified by E. Do not shift 
bit 0. If £ is positive, shift left bringing Os into bit 35; data shifted out of bit 
1 is lost; set Overflow if any bit of significance is lost (a 1 in a positive num- 
ber, a in a negative one). If E is negative, shift right bringing Os into bit 1 
if AC is positive, Is if negative; data shifted out of bit 35 is lost. 



50 



2-32 



CENTRAL PROCESSOR 



§2.6 



ASHC 



Arithmetic Shift Combined 



Left: 2.0Q(2.11) + .15|£:1ms 
Right: 1.84(1.95) + .151^1 MS 



244 


A 


I 


X 


Y 



12 13 14 



17 18 



35 



Concatenate the magnitude portions of accumulators A and ^ + 1 with A on 
the left, and shift the 70-bit combination in bits 1-35 and 37-71 the num- 
ber of places specified by E. Do not shift AC bit 0, but make bit of AC 
A + l equal to it if at least one shift occurs (ie if E is nonzero). If £ is posi- 
tive; shift left bringing Os into bit 71 (bit 35 of AC A + 1); bit 37 (bit 1 of AC 
y4+l) is shifted into bit 35; data shifted out of bit 1 is lost; set Overflow if 
any bit of significance is lost (a 1 in a positive number, a in a negative one). 
If E is negative, shift right bringing Os into bit 1 if AC is positive. Is if nega- 
tive; bit 35 is shifted into bit 37; data shifted out of bit 71 is lost. 



2.6 FLOATING POINT ARITHMETIC 



A subtraction involving two 
like-signed numbers whose 
exponents are equal and 
whose fractions differ only in 
the LSB gives a result con- 
taining only one bit of signi- 
ficance. 



For floating point arithmetic the PDF- 10 has instructions for scaling the 
exponent (which is multiplication of the entire number by a power of 2) 
and negating double length numbers as well as for performing addition, sub- 
traction, multiplication and division of numbers in floating point format. 
All instructions treated here interpret all operands as floating point numbers 
in the format given in § 1.1, and generate results in that format. The reader 
is strongly advised to reread §1.1 if he does not remember the format in 
detail. 

For the four standard arithmetic operations the program can select wheth- 
er or not the result shall be rounded. Rounding produces the greatest con- 
sistent precision using only single length operands. Instructions without 
rounding have a "long'* mode, which supplies a two- word result for greater 
precision; the other modes save time in one-word operations where rounding 
is of no significance. 

Actually the result is formed in a double length register in addition, sub- 
traction and multiplication, wherein any bits of significance in the low order 
part' supply information for normalization, and then for rounding if re- 
quested. Consider addition as an example. Before adding, the processor 
right shifts the fractional part of the operand with the smaller exponent until 
its bits correctly match the bits of the other operand in order of magnitude. 
Thus the smaller operand could disappear entirely, having no effect on the 
result ("result*' shall always be taken to mean the information (one word or 
two) stored by the instruction, regardless of the number of significant bits it 
contains or even whether it is the correct answer). Long mode is likely to 
retain information that would otherwise be lost, but in any given mode the 
significance of the result depends on the relative values of the operands. 
Even when both operands contain twenty -seven significant bits, a long addi- 
tion may store two words that together contain only one significant bit. In 
division the processor always calculates a one-word quotient that requires no 



51 



§2.6 



FLOATING POINT ARITHMETIC 



2-33 



nonnalization if the original operands are normalized. An extra quotient bit 
is calculated for rounding when requested; long mode retains the remainder. 

The processor has four flags, Overflow, Floating Overflow, Floating 
Underflow and No Divide, that indicate when the exponent is too large or 
too small to be accommodated or a division cannot be performed because of 
the relative values of dividend and divisor. Any of these circumstances sets 
Overflow and Floating Overflow, If only these two are set, the exponent of 
the answer is too large; if Floating Underflow is also set, the exponent is too 
small. No Divide being set means the processor failed to perform a division, 
an event that can be produced only by a zero divisor if all nonzero operands 
are normalized. These flags can be read and controlled by certain program 
control instructions [§2.9], and Overflow and Floating Overflow are avail- 
able as processor conditions (via in-out instructions [§2.14]) that can 
request a priority interrupt if enabled. The conditions detected can only set 
the flags and the hardware does not clear them, so the program must clear 
them before a floating point instruction if they are to give meaningful infor- 
mation about the instruction afterward. However, the program can check 
the flags following a series of instructions to determine whether the entire 
series was free of the types of error detected. 

The floating point hardware functions at its best if given operands that 
are either normalized or zero, and except in special situations the hardware 
normalizes a nonzero result. An operand with a zero fraction and a nonzero 
exponent can give wild answers in additive operations because of extreme 
loss of significance; eg adding Vi X 2^ and X 2^^ gives a zero result, as the 
first operand (having a smaller exponent) looks smaller to the processor and 
is shifted to oblivion. A number with a 1 in bit and Os in bits 9-35 is not 
simply an incorrect representafion of zero, but rather an unnormalized 
"fraction" with value - 1 . This unnormalized number can produce an incor- 
^rect answer in any operation. Use of other unnormalized operands simply 
causes loss of significant bits, except in division where they can prevent its 
execution because they can satisfy a no-divide condition that is impossible 
for normalized numbers. 



The processor normalizes the 
result by shifting the fraction 
and adjusting the exponent to 
compensate for the change in 
value. Each shift and accom- 
panying exponent adjustment 
thus multiply the number 
both by 2 and by H simulta- 
neously, leaving its value un- 
changed. 



Scaling 

One floating point instruction is m a category by itself: it changes the 
exponent of a number without changing the significance of the fraction. In 
other words it multiplies the number by a power of 2, and is thus analogous 
to arithmetic shifting of fixed pomt numbers except that no information is 
lost, although the exponent can overflow or underflow. The amount added 
to the exponent is specified by the result of the effective address calculation 
taken as a signed number (in twos complement notation) modulo 2^ in mag- 
nitude. In other words the effective scale factor E is the number composed 
of bit 18 (which is the sign) and bits 28-35 of the calculation result. Hence 
the programmer may specify the factor directly in the instruction (perhaps 
indexed) or give an indirect address to be used in calculating it. A positive E 
increases the exponent, a negative E decreases it; £ is thus the power of 2 by 
which the number is multiplied. The scale factor lies in the range -256 to 
+255. 



52 



2-34 



CENTRAL PROCESSOR 



§2.6 



TV is the number of left shifts 
needed to normalize the 
result. 



Ihis instruction can be used 
to float a fixed number with 
27 or fewer significant bits. 
To float an integer contained 
within AC bits 9-35, 

FSC AC,233 

inserts the correct exponent 
to move the binary point 
from the right end to the left 
of bit 9 and then normalizes 
(2338 = l55io= 128 + 27). 



FSC 



Floating Scale 



2.75 (2.86) + .25iV MS 



132 1 A 


7 


X 


Y 



89 



12 13 14 



17 18 



35 



If the fractional part of AG is zero, "clear AC. Otherwise add the scale factor 
given by E to the exponent part of AC (thus multiplying AC by 2^, normal- 
ize the resulting word bringing Os into bit positions vacated at the right, and 
place the result back in AC. 

Note 

A negative E is represented in standard twos com- 
plement notation, but the hardware compensates 
for this when scaling the exponent. 

If the exponent after normalization is > 127, set Overflow and Floating 
Overflow; the result stored has an exponent 256 less than the correct one. 
If < -128, set Overflow, Floating Overflow and Floating Underflow; the 
result stored has an exponent 256 greater than the correct one. 



In the hardware the rounding 
operation is actually some- 
what more complex than 
stated here. If the result is 
negative, the hardware com- 
bines rounding with placing 
the high order word in twos 
complement form by decreas- 
ing its magnitude if the low 
order part is < ^LSB. More- 
over an extra single-step re- 
normalization occurs if the 
rounded word is no longer 
normalized. 

Keeping instructions and op- 
erands in different memories 
saves .47 (.36) /is in memory 
and both modes. 

When E addresses a fast 
memory location, a floating 
point instruction with round- 
ing takes .34 jus less than the 
time listed in basic mode, .80 
(.69) tis less in memory or 
both mode. 



Operations with Rounding 

There are four instructions that use only one-word operands and store a 
single-length rounded result. Rounding is away from zero: if the part of the 
normalized answer being dropped (the low order part of the fraction) is 
greater than or equal in magnitude to one half the LSB of the part being 
retained, the magnitude of the latter part is increased by one LSB. 

The rounding instructions have four modes that determine the source of 
the non-AC operand and the destination of the result. These modes are like 
those of logic and fixed point arithmetic, including an immediate mode that 
allows the instruction to carry an operand with it. 



Mode 


Suffix 


Source ofnon- ' 
AC operand 


Destinatiof 
of result 


Basic 




E 


AC 


A Immediate 


I 


The word £",0 


AC 


Memory 


M 


E 


E 


Both 


B 


E , 


AC and E 



Note however that floating point immediate uses £,0 as an operand, not 
0, E. In other words the half word E is interpreted as a sign, an 8-bit expo- 
nent, and a 9-bit fraction. 

The time required is a function of the number N of left shifts needed for 
normalization. Brackets enclose the additional time required when rounding 
actually changes the high order word. 

In each of these instructions, the exponent that results from normaliza- 



53 



§2.6 



FLOATING POINT ARITHMETIC 



2-35 



tion and rounding is tested for overflow or underflow. If the exponent is 
> 127, set Overflow and Floating Overflow; the result stored has an expo- 
nent 256 less than the correct one. If < - 1 28, set Overflow, Floating Over- 
flow and Floating Underflow; the result stored has an exponent 256 greater 
than the correct one. 



FADR 



Floating Add and Round 



144 



M 



67 89 



12 13 14 



1718 



3S 



Floating add the operand specified by M to AC. If the double length fraction 
in the sum is zero, clear the specified destination. Otherwise normalize the 
double length sum bringing Os into bit positions vacated at the right, round 
the high order part, test for exponent overflow or underflow as described 
above, and place the result in the specified destination. 

FADR Floating Add and Round 144 

4.46 (4.68) + ASD -I- .257V [+.96] /is 
FADR I Floating Add and Round Immediate 145 

3.70 (3.81) + .15Z) + .25A^ [+.96] MS 
FADRM Floating Add and Round to Memory 146 

5.43 (5.65) + .15Z) + .257V [+.96] JUS 
FADRB Floating Add and Round to Both 147 

5.43 (5.65) + .15Z) + .25A^ [+.96] MS 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise Z) = 0. 



FSBR 



154 



Floating Subtract and Round 



M 



67 89 



12 13 14 



17 18 



35 



Floating subtract the operand specified by M from AC. If the double length 
fraction in the difference is zero, clear the specified destination. Otherwise 
normalize the double length difference bringing Os into bit positions vacated 
at the right, round the high order part, test for exponent overflow or under- 
flow as described above, and place the result in the specified destination. 

FSBR Floating Subtract and Round 154 

4.64 (4.86) + .15£> + .15A^ [+.96] MS 
FSBRI Floating Subtract and Round ImmSdiate 155 

3.88 (3.99) + ASD + .15A^ [+.96] ms 
Floating Subtract and Round to Memory 156 

5.61 (5.83) + ASD + .157V [+.96] ms 
FSBRB Floating Subtract and Round to Both 157 

5.61 (5.83) + .15Z) + .15A^ [+.96] MS 



FSBRM 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise Z) = 0. 



54 



2-36 



CENTRAL PROCESSOR 



§2.6 



FMPR 



Use of normalized operands 
requires at most one normali- 
zation step for the result. If 
unnormalized operands are 
used, all times must be in- 
creased by .25N. 



Floating Multiply and Round 



164 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating Multiply AC by the operand specified by M. If the double length 
fraction in the product is zero, clear the specified destination. Otherwise 
normalize the double length product bringing Os into bit positions vacated at 
the right, round the high order part, test for exponent overflow or underflow 
as described above, and place the result in the specified destination. 

FMPR Floating-Multiply and Round 164 

10.29(10.51) [+.96] MS 

FMPRI Floating Multiply and Round Immediate 165 

8.36(8.47) [+.96] fis 

FMPRM Floating Multiply and Round to Memory 166 

11.26(11.48) [+.96] MS 

FMPRB Floating Multiply and Round to Both 167 

11.26(11.48) [+.96] MS 

Timing. The times given above are average for normalized operands. 
Refer to the description of MUL [ § 2.5] for the timing effects of the multi- 
plication algorithm. Minimum times with a zero multiplier are 



FMPR 
FMPRI 
FMPRM 
FMPRB 



8.47 (8.69) [+.96] ms 
7.71 (7.82) [+.96] ms 
9.44(9.66) [+.96] ms 
9.44(9.66) [+.96] ms 



These must be increased by . 1 3 ms for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



Division fails if the divisor is 
zero, but the no-divide condi- 
tion can otherwise be satisfied 
only if at least one operand is 
unnormalized. 



FDVR 



Floating Divide and Round 



174 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



35 



If the magnitude of the fraction in AC is greater than or equal to twice that 
of the fraction in the operand specified by M, set Overflow, Floating Over- 
flow and No Divide, and go immediately to the next instruction without 
affecting the original AC or memory operand in any way. 

If the division can be performed, floating divide AC by the operand spec- 
ified by Af, calculating a quotient fraction of 28 bits (this includes an extra 
bit for rounding). If the fraction is zero, clear the specified destination. 
Otherwise round the fraction using the extra bit calculated. 
If the original operands were normalized, the single length 
quotient will already be normalized; if it is not, normalize 
it bringing Os into bit positions vacated at the right. Test for 



55 



§2.6 



FLOATING POINT ARITHMETIC 



exponent overflow or underflow as described above, and place the result in 
the specified destination. 



FDVR Floating Divide and Round 

FDVRI Floating Divide and Round Immediate 

FDVRM Floating Divide and Round to Memory 

FDVRB Floating Divide and Round to Both 



174 
14.1 (14.3) MS 

175 
13.3 (13.4) ius 

176 
15.1 (15.3) MS 

177 
15.1 (15.3) MS 



2-37 



If unnomialized operands are 
used, all times must be in- 
creased by ,2SN. If the divi- 
sion is not performed, only 
3.5-4 MS are required. 



Operations without Rounding 

Instructions that do not round are faster for processing floating point num- 
bers with fractions containing fewer than 27 significant bits. On the other 
hand the long mode provides double precision or allows the programmer to 
use his own method of rounding. Besides the four usual arithmetic opera- 
tions with normalization, there are two nonnormalizing instructions that 
facilitate double precision arithmetic [ §2. 1 1 gives examples of double preci- 
sion floating point routines] . These two instructions have no modes. 



DFN 



Double Floating Negate 



3.43 (3:54) MS 



131 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Negate the double length floating point number composed of the contents of 
AC and location E with AC on the left. Do this by taking the twos comple- 
ment of the number whose sign is AC bit 0, whose exponent is in AC bits 
1-8, and whose fraction is the 54-bit string in bits 9-35 of AC and location 
E. Place the high order word of the result in AC; place the low order part of 
the fraction in bits 9-35 of location E without altering the original contents 
of bits 0-8 of that location. > 



Usually the double length 
number is in two adjacent 
accumulators, and E equals 
^+1. In this case DFN takes ▲ 
only 2.89 (3.11) MS. 



UFA 



Unnormalized Floating Add 



4.62 (4.84) + .15/) MS 



130 



89 



12 13 14 



17 18 



Floating add the contents of location E to AC. If the double length fraction 
in the sum is zero, clear accumulator ^+1. Otherwise normalize the sum 
only if the magnitude of its fractional part is ^ 1 , and place the high order 
part of the result in AC A-\-\. The original contents of AC and E are 
unaffected. 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise D = 0. 

When E addresses a fast 
memory location, UFA takes 
.34 MS less than the time 
given. 



56 



2-38 



CENTRAL PROCESSOR 



§2.6 



The exponent of the sum is 
^ equal to that of the larger 

summand unless addition of 
^ the fractions overflows, in 

which case it is greater by 1 . 

Exponent overflow can occur 

only in the latter case. 



Note 

The result is placed in accumulator A-f-l. This is 
the only arithmetic instruction that stores the 
result in a second accumulator, leaving the original 
operands intact. 

If the exponent of the sum following the one-step normalization is > 127, 
set Overflow and Floating Overflow; the result stored has an exponent 256 
less than the correct one. 



The renlaining floating point instructions perform the four standard arith- 
metic operations with normalization but without rounding. All use AC and 
the contents of location E as operands and have four modes. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) ^s in memory 
and both modes. 

When E addresses a fast 
memory location, a floating 
point instruction without 
rounding takes .34 ms less 
than the time listed in basic 
or long mode, .80 (.69) jus 
less in memory or both mode. 



Mode 


Suffix 


Basic 




Long 


L 



Memory 
Both 



Effect 
High order word of result stored in AC. 
In addition, subtraction and multiplica- 
tion, the two-word result (in the double 
length format described in §1.1), is 
stored in accumulators A and ^ + 1 . In 
division the dividend is the double length 
word in A and A + l; the single length 
quotient is stored in AC, the remainder 
inAC^ + 1. 

High order word of result stored in E. 
High order word of result stored in AC 
and E. 



In each of these instructions, the exponent that results from normaliza- 
tion is tested for overflow or underflow. If the exponent is > 127, set Over- 
flow and Floating Overflow; the result stored has an exponent 256 less than 
the correct one. If < -128, set Overflow, Floating Overflow and Floating 
Underflow; the result stored has an exponent 256 greater than the correct 
one. 

The time required is a function of the number N of left shifts needed for 
normalization. 



FAD 



Floating Add 



1 140 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Floating add the contents of location E to AC. If the double length fraction 
in the sum is zero, clear the destination specified by M, clearing both accu- 



57 



§2.6 



BLOATING POINT ARITHMETIC 



2-39 



mulators in long mode. Otherwise normalize the double length sum bringing 
Os into bit positions vacated at the right, test for exponent overflow or 
underflow as described above, and place the high order word of the result in 
the specified destination. 

In long mode if the exponent of the sum is > 154 (127 + 27) or < -101 
(-128 + 27) or the low order half of the fraction is zero, clear AC^+1. 
Otherwise place a low order word for a double length result in ^ + 1 by 
putting a in bit 0, an exponent in positive form 27 less than the exponent 
of the sum in bits 1-8, and the low order part of the fraction in bits 9-35. 



FAD . Floating Add 
FAD L Floating Add Long 

FADM Floating Add to Memory 

F A D B Floating Add to Both 



140 
4.46 (4.68) + .15Z) + .25A^ MS 

141 
5.31(5.53) + .15Z) + .25A^MS 

142 
5.43 (5.65) + .15D + .25A^ MS 

143 
5.43 (5.65) + .15£) + .25A^ MS 



D is the difference between 
the operand exponents pro- 
vided that difference is < 63. 
Otherwise D — 0. 



FSB 



Floating Subtract 



150 


M 


A 


I X 


1 



67 89 



12 13 14 



17 18 



35 



Floating subtract the contents of location E from AC. If the double length 
fraction in. the difference is zero, clear the destination specified by Af, clear- 
ing both accumulators in long mode. Otherwise normalize the double length 
difference bringing Os into bit positions vacated at the right, test for expo- 
nent overflow or underflow as described above, and place the high order 
word of the result in the specified destination. 

In long mode if the exponent of the difference is > 154 (127 + 27) or 
< -101 (-128 + 27) or the low order half of the fraction is zero, clear AC 
v4+ 1 . Otherwise place a low order word for a double length result in ^ + 1 by 
putting a in bit 0, an exponent in positive form 27 less than the exponent 
of the difference in bits 1 -8, and the low order part of the fraction in bits 
9-35. 



FSB Floating Subtract 

FSBL Floating Subtract Long 

FSBM Floating Subtract to Memory 

FSBB Floating Subtract to Both 



150 
4.64(4.86) + .15D + .25Afjus 

151 
5.49 (5.71) + .15£) + .25A^ MS 

152 
5.61 (5.83) + .15Z) + .25A^ MS 

153 
5.61 (5.83) + .15D + . 257V MS 



D is the difference between 
the operand exponents pro- 
vided that difference is <63. 
Otherwise Z> = 0. 



58 



2-40 



CENTRAL PROCESSOR 



§2.6 



FMP 



Floating Multiply 



160 


M 


A 


I 


X 


Y 



12 13 14 



35 



Use of normalized operands 
requires at most one normali- 
zation step for the result. If 
unnormalized operands are 
used, all times must be in- 
creased by .257V. 



Floating multiply AC by the contents of location E. If the double length 
fraction in the product is zero, clear the destination specified by M, clearing 
both accumulators in long mode. Otherwise normalize the double length 
product bringing Os into bit positions vacated at the right, test for exponent 
overflow or underflow as described above, and place the high order word of 
the result in the specified destination. 

In long mode if the exponent of the product is > 154 (127 + 27) or 
< -101 (-128 + 27) or the low order half of the fraction is zero, clear AC 
^+1. Otherwise place a low order word for a double length result in A + 1 
by putting a in bit 0, an exponent in positive form 27 less than the 
exponent of the product in bits 1-8, and the low order part of the fraction 
in bits 9-35. 



FMP 


Floating Multiply 


160 


10.29 (10.51) MS 


FMPL 


Floating Multiply Long 


161 


11.14 (11.36) MS 


FMPM 


Floating Multiply to Memory 


162 


11.26 (11.48) MS 


FMPB 


Floating Multiply to Both 


163 


11.26 (11.48) MS 



Timing. The times given above are average for normalized operands. 
Refer to the description of MUL [ §2.5] for the timing effects of the multi- 
plication algorithm. Minimum times with a zero multiplier are 



FMP 


8.47 (8.69) MS 


FMPL 


9.32 (9.54) MS 


FMPM 


9.44 (9.66) MS 


FMPB 


9.44 (9.66) MS 



These must be increased by .13 ms for each transition. The programmer can 
minimize the time by using as the multiplier the operand with fewer transi- 
tions. 



FDV 



Floating Divide 



170 


M 


A 


I 


X 


Y 



67 89 



12 13 14 



17 18 



35 



Division fails if the divisor is 
zero, but the no-divide condi- 
tion can otherwise be satisfied 
only if at least one operand is 
unnormalized. 



If the magnitude of the fraction in AC is greater than or equal to twice that 
of the fraction in location E, set Overflow, Floating Overflow and No Divide, 
and go immediately to the next instruction without affecting the original AC 
or memory operand in any way. 

If division can be performed, flo<lting divide the AC operand by the 
cqntents of location E. In long mode the AC operand (the dividend) is the 
double length number in accumulators A and ^ + 1 ; in other modes it is the 
single word in AC, Calculate a quotient fraction of 27 bits. If the fraction 



59 



§2.7 



ARITHMETIC TESTING 



2-41 



is zero, clear the destination specified by M, clearing both accumulators in 
long mode if the double length dividend was zero. A quotient with a non- 
zero fraction will already be normalized if the original operands were nor- 
malized; if it is not, normalize it bringing Os into bit positions vacated at the 
right. Test for exponent overflow or underflow as described above, and 
place the single length quotient part of the result in the specified destination. 
In long mode calculate the exponent for the fractional remainder from the 
division according to the relative magnitudes of the fractions in dividend and 
divisor: if the dividend was greater than or equal to the divisor, the exponent 
of the remainder is 26 less than that of the dividend, otherwise it is 27 less. 
If the remainder exponent is > 127 or < -128 or the fraction is zero, clear 
AC A + l. Otherwise place the floating point.remainder (exponent and frac- 
tion) with the sign of the dividend in AC A-\-\. 



FDV 


Floating Divide 


170 


14.1 (14.3) JUS 


FDVL 


Floating Divide Long 


171 


15.6 (15.8) MS 


FDVM 


Floating Divide to Memory 


172 


15.1 (15.3) MS 


FDVB 


Floating Divide to Both 


173 


15.1 (15.3) MS 



In long mode a nonzero un- 
normalized dividend whose 
entire high order fraction is 
zero produces a zero quo- 
tient. In this case the second 
AC receives rubbish. 



If unnormalized operands are 
used, all times must be in- 
creased by .25N. If the divi- 
sion is not performed, only 
4-4.5 MS are required. 



2.7 ARITHMETIC TESTING 

These instructions may jump or skip depending on the result of an arithmetic 
test and may first perform an arithmetic operation on the test word. Two of 
the instructions have no modes. 



AOBJP 



Add One to Both Halves of AC and Jump if Positive 



1.68 (1.79) MS 



252 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Add 1 000001 8 to AC and place the result back in AC. If the result is greater 
than or equal to zero {ie if bit is 0, and hence a negative count in the left 
half has reached zero or a positive count has not yet reached 2^"^), take the 
next instruction from location E and continue sequential operation from 
there. 



AOBJN 



Add One to Both Halves of AC and Jump if Negative 1 .68 ( 1 .79) ms 



253 


A 


I 


X 


Y 



89 



12 13 14 



35 



Add 1 000001 8 to AC and place the result back in AC. If the result is less 
than zero {ie if bit is 1 , and hence a negative count in the left half has not 
yet reached zero or a positive count has reached 2^''), take the next instruc- 
tion from location E and continue sequential operation from there. 



2-42 



60 

CENTRAL PROCESSOR 



§2.7 



The incrementing of both halves of AC simultaneously is effected by adding 
1 00000 Ig. A count of -2 in AC left is therefore increased to zero if 2^* - 1 
is incremented in AC right. 

Th^se two instructions allow the program to keep a control count in the 
left half of an index register and require only one data transfer to initialize. 
Problem; Add 3 to each location in a table of N entries starting at TAB. 
Only four instructions are required. 

MOVSI XR,-N ;Put -A^ in XR left (clear XR right) 

MOVEI AC, 3 ;Put3inAC 

ADDM AC,TAB(XR) ;Add 3 to entry 
AOBJN XR,.-1 ;Update XR and go back unless all 

; entries accounted for 



The eight remaining instructions jump or skip if the Operand or operands 
satisfy a test condition specified by the mode. 



Mode 


Sufft 


Never 




Less 


L 


Equal 


E 


Less or Equal 


LE 


Always 


A 


Greater or Equal 


GE 


Not Equal 


N 


Greater 


G 



Instructions with one operand compare AC or the contents of location E 
with zero, those with two compare AC with E or the contents of location £. 
The processor always makes the comparison even though the result is used in 
only six of the modes. If the mnemonic has no suffix there is never any 
program control function, and the instruction may be a no-op; an A suffix 
produces an unconditional jump or skip - the action is always taken regard- 
less of how the two quantities compare. 



CAI Compare AC Immediate and Skip if Condition 

Satisfied 



1.68 (1.79) JUS 



Z] 



30 



M 



56 



89 



12 13 14 



17 18 



35 



Compare AC with E {ie with the word p,£) and skip the next instruction in 
sequence if the condition specified by M is satisfied. 



61 



§2.7 



ARITHMETIC TESTING 



2^3 



CAl 


Compare AC Immediate but Do Not Skip 


CAIL 


Compare AC Immediate and Skip if AC Less than E 


CAIE 


Compare AC Immediate and Skip if Equal 


CAILE 


Compare AC Immediate and Skip if AC Less than 
or Equal to E 


CAIA 


Compare AC Immediate but Always Skip 


CAIGE 


Compare AC Immediate and Skip if AC Greater than 
or Equal to E 


CAIN 


Compare AC Immediate and Skip if Not Equal 


CAl 6 


Compare AC Immediate and Skip if AC Greater than E 



300 
301 
302 
303 

304 
305 

306 
307 



CAl is a no-op. 



CAM Compare AC with Memory and Skip if Condition 2.53 (2.75) //s 

Satisfied 



31 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Compare AC with the contents of location E and skip the next instruction in 
sequence if the condition specified by M is satisfied. The pair of numbers 
compared may be either both fixed or both normalized floating point. 

CAM Compare AC with Memory but Do Not Skip 

CAML Compare AC with Memory and Skip if AC Less 

CAME Compare AC with Memory and Skip if Equal 

CAMLE Compare AC with Memory and Skip if AC Less 

or Equal 

CAMA Compare AC with Memory but Always Skip 

CAMGE Compare AC with Memory and Skip if AC Greater 

or Equal 
CAMN Compare AC with Memory and Skip if Not Equal 

CAMG Compare AC with Memory and Skip if AC Greater 



When E addresses a fast mem- 
ory location, this instruction 
takes .34 y& less than the time 
given. 



310 


CAM is a no-op that refer- 


311 


ences memory. 


312 




313 




314 




315 




316 




317 





JUMP 



Jump if AC Condition Satisfied 



1.68 (1.79) MS 



32 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



35 



Compare AC (fixed or floating) with zero, and if the condition specified by 
M is satisfied, take the next instruction from location E and continue 
sequential operation from there. 

JUMP Do Not Jump 320 

JUMPL Jump if AC Less than Zero . 321 

JUMPE Jump if AC Equal to Zero 322 



JUMP is a no-op (instruction 
code 320 has this mnemonic 
for symmetry). 



62 



2-44 



CENTRAL PROCESSOR 

JUMPLE Jump if AC Less than or Equal to Zero 

JUMPA Jump Always 

JUMPGE Jump if AC Greater than or Equal to Zero 

JUMPN Jump if AC Not Equal to Zero 

JUMPG Jump if AC Greater than Zero 



§2.7 

323 
324 

325 
326 

327 



When E addresses a fast mem- 
ory location, this instruction 
takes .34 /us less than the time 
given. 

If >1 is zero, SKIP is a no-op; 
otherwise it is equivalent to 
MOVE. (Instruction code 330 
has mnemonic SKIP for sym- 
metry.) 



SKIPA is a convenient way to 
load an accumulator and skip 
over an instruction upon en- 
tering a loop. 



SKIP 



Skip if Memory Condition Satisfied 



2.39 (2.61) MS 



33 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Compare the contents (fixed or floating) of location E with zero, and skip 
the next instruction in sequence if the condition specified by M is satisfied. 
If ^ is nonzero also place the contents of location E in AC. 



SKIP Do Not Skip 

SKI PL Skip if Memory Less than Zero 

SKIPE Skip if Memory Equal to Zero 

SKIPLE Skip if Memory Less than or Equal to Zero 

SKIPA Skip Always 

SKlPGf Skip if Memory Greater than or Equal to Zero 

SKIPN Skip if Memory Not Equal to Zero 

SKIPG Skip if Memory Greater than Zero 



330 
331 
332 
333 
334 
335 
336 
337 



AOJ 



Add One to AC and Jump if Condition Satisfied 



56 



89 



12 13 14 



17 18 



1.68 (1.79) MS 



34 


M 


A 


I 


X 


Y 



Increment AC by one and place the result back in AC. Compare the result 
with zero, and if the condition specified by M^h satisfied, take the next in- 
struction from location E and continue sequential operation from there. If 
AC originally contained 2^^- 1, set the Overflow and Carry 1 flags; if -1, 
set Carry and Carry 1 . 

AOJ Add One to AC but Do Not Jump ' 340 

AOJL Add One to AC and Jump if Less than Zero 34 1 

AOJE Add One to AC and Jump if Equal to Zero 342 

AOJLE Add One to AC and Jump if Less than or Equal to Zero 343 

AOJA Add One to AC and Jump Always 344 

AG JG E Add One to AC and Jump if Greater than or Equal 345 

to Zero 

AGJN Add One to AC and Jump if Not Equal to Zero 346 

AG JG Add One to AC and Jump if Greater than Zero 347 



63 



§2.7 



ARITHMETIC TESTING 



2-45 



AOS 



Add One to Memory and Skip if Condition Satisfied 2.94 (3.05) tis 



35 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Increment the contents of location E by one and plajce the result back in E, 
Compare the result with zero, and skip the next instruction in sequence if 
the condition specified by M is satisfied. If location E originally contained 
2^^ — 1, set the Overflow and Carry 1 flags; if —1, set Carry and Carry 1. 
If ^ is nonzero also place the result in AC. 



ADS 


Add One to Memory but Do Not Skip 


350 


AOSL 


Add One to Memory and Skip if Less than Zero 


351 


AOSE 


Add One to Memory and Skip if Equal to Zero 


352 


AOSLE 


Add One to Memory and Skip if Less than or Equal 
to Zero 


353 


AOSA 


Add One to Memory and Skip Always 


354 


AOSGE 


Add One to Memory and Skip if Greater than or 
Equal to Zero - 


355 


AOSN 


Add One to Memory and Skip if Not Equal to Zero 


356 


AOSG 


Add One to Memory and Skip if Greater than Zero 


357 



Keeping the count in fast 
memory saves .54 (.43) jus; 
keeping it in a different mem- 
ory from the instruction saves 
.20(.09)ius. 



SO J Subtract One from AC and Jump if Condition 

Satisfied 



1.68 (1.79) MS 



36 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17 18 



35 



Decrement AC by one and place the result back in AC. Compare the result 
with zero, and if the condition specified by M is satisfied, take the next in- 
struction from location E and continue sequential operation from there. If 
AC originally contained -2^^, set the Overflow and Carry flags; if any other 
nonzero number, set Carry and Carry 1 . 

but Do Not Jump 360 

and Jump if Less than Zero 361 

and Jump if Equal to Zero 362 

and Jump if Less than or 363 

and Jump Always 364 

and Jump if Greater than or 365 

and Jump if Not Equal to Zero 366 

and Jump if Greater than Zero 367 



SOJ 


Subtract One from AC 


SOJL 


Subtract One from AC 


SOJE 


Subtract One from AC 


SOJLE 


Subtract One from AC 




Equal to Zero 


SOJA 


Subtract One from AC 


SOJGE 


Subtract One from AC 




Equal to Zero 


SOJN 


Subtract One from AC 


SOJG 


Subtract One from AC 



2-46 

Keeping the count in fast 
memory saves .54 (.43) jus; 
keeping it in a different mem- 
ory from the instruction saves 
.20 (.09) MS. 



SOS 



64 



CENTRAL PROCESSOR §2.7 

Subtract One from Memory and Skip if Condition 2.94 (3.05) //s 

Satisfied 



37 


M 


A 


I 


X 


Y 



56 



89 



12 13 14 



17.18 



3S 



Decrement the contents of location E by one and place the result back in E. 
Compare the result with zero, and skip the next instruction in sequence if 
the condition specified by M is satisfied. If location E originally^ contained 
-2^^, set the Overflow and Carry flags; if any other nonzero number, set 
Carry arid Carry 1 . Jf ^ is nonzero also place the result in AC. 

SOS Subtract One from Memory but Do Not Skip 370 

SOSL Subtract One from Memory and Skip if Less than Zero 371 

SOSE Subtract One from Memory and Skip if Equal to Zero 372 

SOSLE Subtract One from Memory and Skip if Less than or 373 

Equal to Zero 

SOSA Subtract One from Memory and Skip Always 374 

SOSGE Subtract One from Memory and Skip if Greater 375 

than or Equal to Zero 
SOSN Subtract One from Memory and Skip if Not Equal 376 

to Zero 

SOSG Subtract One from Memory and Skip if Greater 377 

than Zero 



Hiis procedure is invalid if 
the programmer is making use 
of the drum split feature 
(which is not used by any 
DEC equipment). 



Some of these instructions are useful for determining the relative values of 
fixed and floating point numbers; others are convenient for controlling 
iterative processes by counting. AOSE is especially useful in an interlock 
procedure in a multiprocessor system. Suppose memory contains a routine 
that must be available to two processors but cannot be used by both at once. 
When one processor finishes the routine it sets location LOCK to - 1 . Either 
processor can then test the interlock and make it busy with no possibility of 
letting the other one in, as AOSE cannot be interrupted once it starts to 
modify the addressed location. 

AOSE LOCK ;Skip to interlocked code only if 

JRST .- 1 ;LOCK is zero after addition 

; Interlocked code starts here 



SETOM LOCK 



[Unlock 



Since it takes several days to count to 2^^, it is alright to keep testing the 
lock. 



65 



§2.8 



LOGICAL TESTING AND MODIFICATION 



2-47 



2.8 LOGICAL TESTING AND MODIFICATION 

These eight instructions use a mask to modify and/or t^st selected bits in 
AC. The bits are those that correspond to Is in the mask and they are 
referred to as the "masked bits". The programmer chooces the mask, the 
way in which the masked bits are to be modified, and the condition the 
masked bits must satisfy to produce a skip. 

The basic mnemonics are three letters beginning with T. The second letter 
selects the mask and the manner in which it is used. 



Mask 


Letter 


Effect 


Right 


R 


AC right is masked by E (AC is masked 
by the word 0,£') 


Left 


L 


AC left is masked by E (AC is masked by 
the word £,0) 


Direct 


D 


AC is masked by the contents of loca- 
tion E 


Swapped 


S 


AC is masked by the contents of loca- 
tion E with left and right halves inter- 
changed 



If a direct or swapped mask is 
taken from a fast memory 
location, a test instruction 
takes .34 y& less than the 
time listed. 



The third letter determines the way in which those bits selected by the mask 
are modified. 



Modification 


Letter 


Effect on AC 


No 


N 


None 


Zeros 


Z 


Places Os in all masked bit positions 


Complement 


C 


Complements all masked bits 


Ones 





Places Is in all masked bit positions 



An additional letter may be appended to indicate the mode, which spec- 
ifies the condition the masked bits must satisfy to produce a skip. 



Mode 
Never 
Equal 
Always 
Not Equal 



Suffix 

E 
A 

N 



Effect 
Never skip 

Skip if :\\ masked bits equal 
Always skip 

Skip if not all masked bits equal 
(at least one bit is 1) 



If the mnemonic has no suffix there is never any skip, and the instruction is 
a no-op if there is also no modification; an A suffix produces an uncondi- 
tional skip - the skip always occurs regardless of the state of the masked 
bits. Note that the skip condition must be satisfied by the state of the 
masked bits prior to any modification called for by the instruction. 



These mode nanies are con- 
sistent with those for arith- 
metic testing and derive from 
the test method, which ands 
AC with the mask and tests 
whether the result is equal to 
zero or is not equal to zero. 
The programmer may find it 
convenient to think of the 
modes as Every and Not 
Every: every masked bit is 
or not every masked bit is 0. 



66 



2-48 



CENTRAL PROCESSOR 



§2.8 



TRN is a no-op. 



TRN Test Right, No Modification, and Skip if Condition 1 .85 ( 1 .96) jlis 

Satisfied 



60 


M 





■ A 


I X 


Y 



56 7 8 9 



12 13 14 



17 18 



If the bits in AC right corresponding to 1 s in £" satisfy the condition specified 
by M, skip the next instruction in sequence. AC is unaffected. 



TRN Test Right, No Modification, but Do Not Skip 

TR N E Test Right , No Modification, and Skip if All 

Masked Bits Equal 

TR N A Test Right, No Modification, but Always Skip 

TR NN Test Right, No Modification, and Skip if Not 

All Masked Bits Equal 



600 
602 

604 
606 



TRZ 



' Test Right, Zeros, and Skip if Condition Satisfied 



1.85 (1.96) MS 



62 



M 



3 



56 7 8 9 



12 13 14 



35 



If the bits in AC right corresponding to Is in ^ satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Os; the rest of AC is unaffected. 



TRZ Test Right, Zeros, but Do Not Skip 

TRZE Test Right, Zeros, and Skip if All Masked Bits 

Equaled 

TRZA Test Right, Zeros, but Always Skip 

TRZN Test Right, Zeros, and Skip if Not All Masked 

Bits Equaled 



620 

622 

624 
626 



TRC Test Right, Complement, and Skip if Condition 1 .85 ( 1 .96) /is 

Satisfied 



64 


M 





A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC right corresponding to Is in ^ satisfy the condition specified 
by M, skip the next instruction in sequence. Complement the masked AC 
bits; the rest of AC is unaffected. 



TRC Test Right, Complement, but Do Not Skip 

TRCE Test Right, Complement, and Skip if All Masked 

Bits Equaled 

TRCA Test R,ight, Complement, but Always Skip 

TRCN Test Right, Complement, and Skip if Not All 

Masked Bits Equaled 



640 
642 

644 
646 



67 



§2.8 • 
TRO 



LOGICAL TESTING AND MODIFICATION 



Test Right, Ones, and Skip if Condition Satisfied 



1.85 (1.96) MS 



6 6 


M 





A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC right corresponding to Is in £" satisfy the condition specified 

by M, skip the next instruction in sequence. Change the masked AC bits to 

Is; the rest of AC is unaffected. 

I 
Test Right, Ones, but Do Not Skip 660 

Test Right, Ones, and Skip if All Masked Bits 662 

Equaled 

Test Right, Ones, but Always Skip 664 

Test Right, Ones, and Skip if Not All Masked 666 

Bits Equaled 



TRO 
TROE 

TROA 
TRON 



2-49 



TLN Test Left, No Modification, and Skip if Condition 1.85(1 .96) jus 

Satisfied 



60 


M 


1 


A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC left corresponding to 1 s in £ satisfy the condition specified 
by M, skip the next instruction in sequence. AC is unaffected. 

TLN Test Left, No Modification, but Do Not Skip 

TLNE TestLeft,NoModification, andSkipif All 

Masked Bits Equal 
TLNA Test Left, No Modification, but Always Skip 

TLNN Test Left, No Modification, and Skip if Not 

All Masked Bits Equal 



601 
603 

605 
607 



TLN is a no-op. 



TLZ 



Test Left, Zeros, and Skip if Condition Satisfied 



56 7 8 9 



12 13 14 



17 18 



1.85 (1.96) MS 



62 


M 


1 


A 


I 


X 


Y 



35 



If the bits in AC left corresponding to 1 s in £" satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
Os; the rest of AC is unaffected. 

621 



TLZ Test Left, Zeros, but Do Not Skip 

TLZE Test Left, Zeros, and Skip if All Masked Bits 

Equaled 
TLZA Test Left, Zeros, but Always Skip 

TLZN Test Left, Zeros, and Skip if Not All Masked 

Bits Equaled 



623 

625 
627 



2-50 



68 

CENTRAL PROCESSOR 

TLC Test Left, Complement, and Skip if Condition 

Satisfied 



§2.8 
1.85 (1.96) jus 



64 



M 1 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC left corresponding to Is in £ satisfy the condition specified 
by M, skip the next instruction in sequence. Complement the masked AC 
bits; the rest of AC is unaffected. 



TLC Test Left, Complement, but Do Not Skip 

TLCE Test Left, Complement, and Skip if All Masked 

Bits Equaled 

TLCA Test Left, Complement, but Always Skip 

TLCN Test Left, Complement, and Skip if Not All 

Masked Bits Equaled 



641 
643 

645 
647 



TLO 



66 



Test Left, Ones, and Skip if Condition Satisfied 



M 



56 7 8 9 



12 13 14 



17 18 



1.85(1. 96) MS 



35 



If the bits in AC left corresponding to Is in £ satisfy the condition specified 
by M, skip the next instruction in sequence. Change the masked AC bits to 
1 s; the rest of AC is unaffected. 



TiO Test Left, Ones, but Do Not Skip 

TLOE Test Left, Ones, and Skip if All Masked Bits 

Equaled 
TLOA Test Left, Ones, but Always Skip 

TLON Test Left, Ones, and Skip if Not All Masked 

Bits Equaled 



661 
663 

665 
667 



TON is a no-op that refer- 
ences memory. 



TON Test Direct, No Modification, and Skip if Condition 

Satisfied 



61 



M 



56 7 8 9 



12 13 14 



17 18 



2.70 (2.92) MS 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by Af, skip the next instruction in sequence. AC is un- 
affected. 



TDN Test Direct, No Modification,^ but Do Not Skip 

TONE Test Direct, No Modification, and Skip if^All 

Masked Bits Equal 
TDN A Test Direct, No Modification, but Always Skip 

TDNN Test Direct, No Modification, and Skip if Not 

All Masked Bits Equal 



610 
612 

614 
616 



69 



§2.8 



LOGICAL TESTING AND MODIFICATION 



2-51 



TDZ 



Test Direct, Zeros, and Skip if Condition Satisfied 



2.70 (2.92) MS 



63 


M 





A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by Af, skip the next instruction in sequence. Change the 
masked AC bits to Os: the rest of AC is unaffected. , 



TDZ Test Direct, Zeros, but Do Not Skip 

TDZE Test Direct, Zeros, and Skip if Ail Masked Bits 

Equaled 
TDZ A Test Direct, Zeros, but Always Skip 

TDZN Test Direct, Zeros, and Skip if Not All Masked 

Bits Equaled 



630 
632 

634 
636 



TDC Test Direct, Complement, and Skip if Condition 2.70 (2.92) us 

Satisfied 



65 


M 


A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC corresponding to Is in the contents of location E satisfy the 
condition specified by My skip the next instruction in sequence. Complement 
the masked AC bits; the rest of AC is unaffected. 



TDC Test Direct, Complement, but Do Not Skip 

TDCE Test Direct, Complement, and Skip if All Masked 

Bits Equaled 
TDCA Test Direct, Complement, but Always Skip 

TDCN Test Direct, Complement, and Skip if Not All 

Masked Bits Equaled 



650 
652 

654 
656 



TDO 



Test Direct, Ones, and Skip if Condition Satisfied 



56 7 8 9 



12 13 14 



17 18 



2.70 (2.92) MS 



67 


M 





A 


I 


X 


! 



35 



If the bits in AC corresponding to 1 s in the contents of location E satisfy the 
condition specified by Af , skip the next instruction in sequence. Change the 
masked AC bits to 1 s; the rest of AC is unaffected.. 



TDO Test Direct, Ones, but Do Not Skip 

TDOE Test Direct, Ones, and Skip if All Masked Bits 

Equaled 
TDO A Test Direct, Ones, but Always Skip 

TOON Test Direct, Ones, and Skip if Not All Masked 

Bits Equaled 



670 
672 

674 
676 



70 



2-52 



TSN is a no-op that refer- 
ences memory. 



CENTRAL PROCESSOR 

TSN Test Swapped, No Modification, and Skip if 

Condition Satisfied 



§2.8 
2.70 (2.92) jus 



61 


M 


1 


A 


I 


X 


Y 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC corresponding to Is in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. AC is unaffected. 



TSN Test Swapped, No Modification, but Do Not Skip 

TSNE Test Swapped, No Modification, and Skip if All 

Masked Bits Equal 

TSNA Test Swapped, No Modification, but Always Skip 

TSNN Test Swapped, No Modification, and Skip if Not 

All Masked Bits Equal 



611 
613 

615 
617 



TSZ 



Test Swapped, Zeros, and Skip if Condition Satisfied 2.70 (2.92) jus 



63 



M 1 



_J 



56 7 8 9 



12 13 14 



17 18 



35 



If the bits in AC corresponding to Is in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. Change the masked AC bits to Os; the rest of 
AC is unaffected. 



TSZ Test Swapped, Zeros, but Do Not Skip 

TSZE Test Swapped, Zeros, and Skip if All Masked Bits 

Equaled 
TSZA Test Swapped, Zeros, but Always Skip 

TSZN Test Swapped, Zeros, and Skip if Not All Masked 

Bits Equaled 



631 
633 

635 
637 



TSC Test Swapped, Complement, and Skip if Condition 2.70 (2.92) jus 

Satisfied 



65 



M |l| 



35 



56 7 8 9 



12 13 14 



17 18 



If the bits in AC corresponding to Is in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. Complement the masked AC bits; the rest of 
AC is unaffected. 



TSC Test Swapped, Complement, but Do Not Skip 

TSCE Test Swapped, Complement, and Skip if All 

Masked Bits Equaled 



651 

653 



71 



§2.8 

TSCA 
TSCN 



LOGICAL TESTING AND MODIFICATION 



Test Swapped, Complement, but Always Skip 
Test Swapped, Complement, and Skip if Not 
All Masked Bits Equaled 



655 
657 



2-53 



ISO 



Test Swapped, Ones, and Skip if Condition Satisfied 



56 7 8 9 



12 13 14 



17 18 



2.70 (2.92) MS 



1 6^ 


M 


1 


A 


I 


X 


Y 



35 



If the bits in AC corresponding to Is in the contents of location E with its 
left and right halves swapped satisfy the condition specified by M, skip the 
next instruction in sequence. Change the masked AC^bits to Is; the rest of 
AC is unaffected. 



ISO Test Swapped, Ones, but Do Not Skip 

TSOE Test Swapped, Ones, and Skip if All Masked Bits 

Equaled 
ISO A Test Swapped, Ones, but Always Skip 

TSON Test Swapped, Ones, and Skip if Not All Masked 

Bits Equaled 



671 
673 

675 
677 



With these instructions any bit throughout all of memory can be used as a 
program flag, although an ordinary memory location containing flags must 
be moved to an accumulator for testing or modification. The usual pro- 
cedure, smce locations 1-17 are addressable as index registers, is to use AC 
as a register of flags (often addressed symbolically as F). 

Unless one frequently tests flags in both halves of F simultaneously, it is 
generally most convenient to select bits by Is right in the address part of the 
instruction word. A given bit selected by a half word mask M is then set by 
one of these: 

TRO ¥,M TLO F,M 

and tested and cleared by one of these: 

TRZE F,M TRZN ¥,M TLZE F,M TLZN F,M 

Suppose we wish to skip if both bits 34 and 35 are 1 in location L. The 
following suffices. 

SETCM F,L 
TRNE F,3 

We can refer to a flag in a given bit position within a word as flag X, where X 
is a binary number containing a single 1 in the same bit position as the flag. 
This sequence determines whether flags X and Y in the right half of accumu- 
lator F are both on: 



2-54 



72 

CENTRAL PROCESSOI^ 



TRC 
TRCE 



F,X+Y 



§2.9 

;Complement flags X and Y 
;Test both and restore original states 
;Do this if not both on 
;Skip to here if both on 



2.9 PROGRAM CONTROL 



As no-ops, code 247 takes 
1.50 (1.61) JUS, 257 takes 
1.36 (1.47.) JUS. 



Note that nothing is stored in 
bits 13-17, so when the PC 
word is addressed indirectly it 
can produce neither indexing 
nor further indirect address- 
ing. 



The program control class of instructions includes the unimplemented user 
operations [discussed in the next section] and the arithmetic and logical test 
instructions. Some instructions in this class are no-ops^ as are a few of the 
instructions for performing logical operations. The most commonly used 
no-op is JFCL, which is discussed below. No-ops among the instructions 
previously discussed are SETA, SETAI, SETMM, CAI, CAM, JUMP, TRN 
TLN, TDN, TSN. Of these, SETA, SETAI, CAI, JUMP, TRN and TLN do 
not use the calculated effective address to reference memory. Hence in these 
instructions one can store any information in bits 18-35 without fear of 
attempting to address a location outside a user block or in a memory that 
does not exist. The unassigned instruction codes 247 and 257 are used for 
mstructions installed specially for a particular system. They execute as 
no-ops when run on a computer that contains no special hardware for them, 
but for program compatibility it is advised that they not be used regularly as 
no-ops. 

The present section treats all program control instructions other than 
those mentioned above and in-out instructions that test input conditions 
[ § 2. 1 2] . All but one of these are jumps, although the exception causes the 
processor to execute an instruction at an arbitrary location and may there- 
fore be regarded as a jump with an immediate and automatic return. Also, 
all but two of the jumps are unconditional; one exception tests various flags, 
the other tests an accumulator. 

Several of the jump instructions save the current contents of the program 
counter PC in the right half of an accumulator or memory location and save 
the states of various flags in the left half. The left bit positions that receive 
mformation are listed below; all other left bit positions are cleared. An Z in 
a mnemonic indicates any letter (or none) that may appear in the given 
position to specify the mode, eg ADDX comprises ADD, ADDI, ADDM, 
ADDB. 

^if Meaning of a 1 in the Bit 

'Overflow - any of the following has occurred: 

A single instruction has set one of the carry flags (bits 1 and 2) 
without setting' the other. 

An ASH or ASHC has left shifted a 1 out of bit 1 in a positive 
number or a out in a negative number. 

An MULZ has multiplied -2^^ by itself (product 2'^^. 

An lUVLX has multiplied two numbers with product > 2^^ or 

<-23s. 



73 



§2-9 



PROGRAM CONTROL 



2-55 



Floating Overflow has been set (bit 3). 

No Divide has been set (bit 1 2). 

Carry ~ if set without Carry 1 (bit 2) being set, causes Overflow to 
be set and indicates that one of the following has occurred: 

An ADVX has added two negative numbers with sum < -2^^. 

An SUBX has subtracted a positive number from a negative num- 
ber with difference < -2^^. 

An SOJX or SOS^ has decremented -2^^ a 

But if set with Carry 1, indicates that one of these nonoverflow 
events has occurred: 

In an ADDA' both summands were negative, or their signs differed 
and their magnitudes were equal or the positive one was the 
greater in magnitude. 

In an SUBX the signs of the operands were the same and AC was 
the greater or the two were equal, or the signs of the operands 
differed and AC was negative. 

An AOJX or AOSX has incremented - 1 . 

An SOJX or SOSAT has decremented a nonzero number other than 

An MOVNAT has negated zero. 

Carry 1 - if set without Carry (bit 1) being set, causes Overflow to 
be set and indicates that one of the following has occurred: 

An ADDAT has added two positive numbers with sum >2^^. 

An SUB^ has subtracted a negative number from a positive num- 
ber with difference > 2^^. 

An AO JJiT or AOS^T has incremented 2^^ - 1 . ^ 

An MOVNX or MOVM^ has negated -2^\ 
But if set with Carry 0, indicates that one of the nonoverflow events 
listed under Carry has occurred. 

Floating Overflow - any of the following has set Overflow: 

In a floating point instruction other than DFN, the exponent of 

the result was > 127. 

Floating Underflow (bit 1 1) has been set. 

No Divide (bit 1 2) has been set in an FD V^ or FDVRJT. 

Byte Interrupt — the processor is in a priority interrupt that inter- 
rupted a byte instruction after the processing of the pointer but 
before the processing of the byte. Hence if an ILDB or IDPB was 
interrupted, the pointer now points not to the last byte, but rather 
to the byte that should be handled upon the return to the inter- 
rupted program [§ 2. 1 3 ] . 

User — the processor is in user mode [§2.151. 



Remember [§2.5] , overflow 
is determined directly from 
the carries, not from the 
flags. The carry flags give 
meaningful information only 
if no more than one instruc- 
tion that can set them occurs 
between clearing and reading 
them. 



74 



2-56 



CENTRAL PROCESSOR 



§2.9 



If normalized operands are 
used, only a zero divisor can 
cause floating division to fail. 



A 6 User In-out - even if the processor is in user mode, no instructions 

are illegal (but protection and relocation still apply) [ §2.15] . 

11 Floating Underflow - in a floating point instruction other than 
DFN, the exponent of the result was < -128 and Overflow and 
Floating Overflow have been set. 

12 No Divide - any of the following has set Overflow: 

In a DYVX the dividend was greater than or equal to the divisor. 

In an IDIVX the divisor was zero. 

In an FDVX or FDVRJT the divisor was zero, or the dividend 
fraction was greater than or equal to twice the divisor fraction in 
magnitude; in either case Floating Overflow has been set. 



OVERFLOW 



FLOATING BYTE 
OVERFLOW INTERRUPT 



FLOATING 
UNDERFLOW 



/ 






J_ 


/ 














/ 














/ 


CARRY 



CARRY ' ' 

1 


/ 


USER 


USER 
IN-OUT 










/ 


NO 
DIVIDE 




















1 


2 


3 


4 


5 


6 


7 


8 


9 


10 


11 


12 


13 


14 


15 


16 


17 



FLAG FORMAT, LEFT HALF OF PC WORD 



The total time required is 
that listed plus the time for 
the instruction executed. If £' 
addresses a fast memory loca- 
tion, the instruction executed 
takes .34 jus less than the time 
listed for it. 



The A portion of this instruc- 
tion is ignored. 



XCT 



Execute 



256 



89 



12 13 14 



17 18 



1.36 (1.47) MS 



35 



Execute the contents of location E as an instruction. Any instruction may 
be executed, includmg another XCT. If an XCT executes a skip instruction, 
the skip is relative to the location of the XCT (the first XCT if there are 
several in a chain). If an XCT executes a jump, program flow is altered as 
specified by the jump (no matter how many XCTs precede a jump instruc- 
tion, when PC is saved it contains an address one greater than the location of 
the first XCT in the chain). 



A^ is the number of leading Os. 



JFFO 



Jump if Find First One 



2. 1 9 (2.30) + .20 (N mod 1 8) jus 



243 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



If AC contains zero, clear AC ^ + 1 and go on to the next instruction in 
sequence. 

If AC is not zero, count the number of leading Os in it (Os to the left of 
the leftmost 1), and place the count mACA-\-\. Take the next instruction 



75 



§2.9 



PROGRAM CONTROL 



2-57 



from location E and continue sequential operation from there. 

In either case AC is unaffected, the original contents of AC ^ + 1 are lost. 



Note that when AC is nega- 
tive, the second accumulator 
is cleared, just as it would be 
if AC were zero. 



JFCL 



Jump on Flag and Clear 



1.36 (1.47) MS 



L 



25 5 



X 



89 



12 13 14 



1718 



35 



If any flag specified by F is set, clear it and take the next instruction from 
location E, continuing sequential operation from there. Bits 9-12 are pro- 
grammed as follows. 



Bit 


Flag Selected by a 1 


9 


Overflow 


10 


Carry 


11 


Carry 1 


12 


Floating Overflow 



To select one or a combination of these flags (which are among those des- 
cribed above) the programmer can specify the equivalent of an AC address 
that places Is in the appropriate bits, but Macro recognizes mnemonics for 
some of the 1 3-bit instruction codes (bits 0-12). 



JFCL 


JFCL 


0, 


No-op 


25500 


JOV 


JFCL 


10, 


Jump on Overflow 


25540 


JCRYO 


JFCL 


4, 


Jump on Carry 


25520 


JCRYl 


JFCL 


2, 


Jump on Carry 1 


25510 


JCRY 


JFCL 


6, 


Jump on Carry or 1 


25530 


JFOV 


JFCL 


1, 


Jump on Floating Overflow 


25504 



This instruction can be used 
simply to clear the selected 
flags by having the jump ad- 
dress point to the next con- 
secutive location, as in 

JFCL 17,. -hi 

which clears all four flags 
without disrupting the nor- 
mal program sequence. A 
JFCL that selects no flag is 
the fastest no-op as it neither 
fetches nor stores an c^erand, 
and bits 18-35 of the instruc- 
tion word can be used to 
store information. 



JSR 



Jump to Subroutine 



2.68 (2.79) fis 



264 


A 


I 


X 


Y 



89 



12 13 14 



35 



Place the current contents of the flags (as described above) in the left half of 
location E and the contents of PC in the right half (at this time PC contains 
an address one greater than the location of the JSR instruction). Take the 
next instruction from location E + 1 and continue sequential operation from 
there. The flags are uiiaffected except Byte Interrupt, which is cleared. 

While the processor is in user mode, if this instruction is executed as an in- 
terrupt instruction or in unrelocated 41 or 61, bit 5 of the PC word stored is 
1 and the processor leaves user mode. 



Interleaving 
.47 (.36) MS. 



memories saves 



The A portion of this instruc- 
tion is ignored. 



76 



2-58 



CENTRAL PROCESSOR 



§2.9 



JSP 



Jump and Save PC 



1.36 (1.47) MS 



1 26 5 


A 


I 


X 


Y 



89 



17 18 



35 



Place the current contents of the flags (as described above) in AC left and 
the contents of PC in AC right (at this time PC contains an address one 
greater than the location of the JSP instruction). Take the next instruction 
from location E and continue sequential operation from there. The flags 
are unaffected except Byte Interrupt, which is cleared. 

While the processor is in user mode, if this instruction is executed as an in- 
terrupt instruction or in unrelocated 41 or 61, bit 5 of the PC word stored is 
1 and the processor leaves user mode. 



JRST 



Jump and Restore 



1.36 (1.47) MS 



- 254 F 


I 


X 


! 



89 



12 13 14 



17 18 



35 



Perform the functions specified by F, then take the next instruction from 
location E and continue sequential operation from there. Bits 9-12 are 
programmed as follows. 



This is identical to UUO trap- 
ping [§2.10]. 



MA actually displays the 
address of the location that 
would have been executed 
next had the JRST been re- 
placed by a no-op. So except 
for a JRST in a priority 
interrupt, MA points to the 
location one beyond that 
containing the instruction 
that caused the halt. This 
instruction is ordinarily the 
JRST or perhaps an XCT, but 
could even be a UUO. 



Bit Function Produced by a 1 

9 Restore the channel on which the highest priority interrupt is cur- 
rently being held [§ 2. 1 3 ] . 

Unless the User In-out flag is set, this function cannot be executed 
in a user program. Instead of restoring the channel, it stores its own 
instruction code, F and effective address E in bits 0-8, 9-12 and 
18-35 respectively of unrelocated location 40 (clearing bits 13-17), 
and then executes the instruction contained in location 4 1 , which is 
under control of the monitor [§2.15]. 

10 Halt the processor. When it stops, the MA lights on the console dis- 
play an address one greater than that of the location containing the 
instruction tjiat caused the halt, and PC displays the jump address 
(the location from which the next instruction will be taken if the 
operator causes the processor to resume operation without changing 
PC). 

Unless the User In-out flag is set, this function cannot be executed 
in a user program. Instead of halting the processor, it stores its 
own instruction code, F and effective address E in Bits 0-8, 9-12 
and 18-35 respectively of unrelocated location 40 (clearing bits 
13-17), and then executes the instruction contained in location 41, 
which is under control of the monitor [§2.15]. 

1 1 Restore the flags listed above from "the left half of the word in the 
last location referenced in the effective address calculation. Hence 
to restore flags requires that the JRST instruction use indexing or 



77 



§2.9 



PROGRAM CONTROL 



2-59 



12 



indirect addressing. 

Restoration of all but the user flags is directly according to the 
contents of the corresponding bits as given above: a flag is set by a 1 
in the bit, cleared by a 0. A 1 in bit 5 sets User but a has no effect, 
so the Monitor can restart a user program by restoring flags but the 
user cannot leave user mode by this method. A in bit 6 clears User 
In-out, but a 1 sets it only if the JRST is being executed by the 
Monitor, ie if User is clear. 

Enter user mode. The user program starts at relocated location E. 



To produce one or a combination of these functions the programmer can 
specify the equivalent of an AC address that places 1 s in the appropriate bits, 
but Macro recognizes mnemonics for the most important 1 3-bit instruction 
codes (bits 0-12). 



JRST 


JRST 


0, 


Jump 


25400 




JRST 


10, 


Jump and Restore 
Interrupt Channel 


25440 


HALT 


JRST 


4, 


Halt 


25420 


JRSTF 


JRST 


2, 


Jump and Restore Flags 


25410 




JRST 


1, 


Jump to User Program 


25404 


JEN 


JRST 


12, 


Jump and Enable 


25450 



In a JRSTF or JEN the flags are restored from bits 0- 1 2 of the final word 
retrieved in the effective address calculation; hence any JRST with a 1 in bit 
1 1 must use indirect addressing or indexing, which takes extra time. If the 
PC word was stored in AC (as in a JSP), a common procedure is to use AC to 
index a zero address (eg, JRSTF (AC)), so its right half becomes the effec- 
tive (jump) address. If the PC word was stored in core (as in a-JSR), one 
must address it indirectly (remember, bits 13-17 of the PC word are clear, 
so again its right half is the effective address). A JRSTF (AC) takes 1.64 
(1.75) JUS, a JRSTF @PCWORD takes 2.34 (2.56) ms. 



By manipulating the contents 
of the left half word used to 
restore the flags, the program- 
mer can set them up in any 
desired way except that a 
user program cannot clear 
User or set User In-out. Set- 
ting Byte Interrupt prevents 
incrementing in the next 
ILDB or IDPB provided there 
is no intervening JSR, JSP or 
PUSHJ. 



JEN completes an interrupt 
by restoring the channel and 
restoring the flags for the 
interrupted program. ^ 



Caution 

Giving a JRSTF or JEN without indexing or 
indirect addressing restores the flags from the 
instruction code itself. 

While the processor is in user mode, if this instruction is executed as an in- ▲ 
temipt instruction or in unrelocated 41 or 61 , bit 5 of the PC word stored is 
1 and the processor leaves user mode. 



JFCL is the only jump that can test any of the flags directly. In fact it is 
the only basic program control instruction that can do so — several of the 
flags can be tested as processor conditions by in-out instructions, but these 
are ordinarily illegal in user programs anyway. But JFCL can test only four 



78 

2-60 CENTRAL PROCESSOR §2.9 

of the flags, and it saves no information for a subsequent return from a sub- 
routine. Hence it serves as a branch point for entry into either one of two 
main paths, which may or may not have a later point in common. Eg, it may 
test the carry flags simply to take appropriate action in a double precision 
fixed point routine. ^ 

JSR and JSP are regularly used to call subroutines. They are uncondi- 
tional, but the execution of such an instruction can be the result of a 
decision made by any conditional skip or jump. In the case of the flags, a 
basic overflow test and subroutine call can be made as follows. 



JOV 


.+2 


JRST 


.+2 


JSR 


OVRFLO 



The fastest skip is CAIA. JRST .+2 ;Faster than skipping 

;Jump over this if pverflow clear 



If we wish to go to the DIVERR routine when No Divide is set, we must first 
read the flags into a test accumulator T and then use a test instruction. 



JSP 


T,. + l 


TLNE 


T,40 


JSR 


DIVERR 



; Store flags but continue in sequence 
;40 left selects bit 12 
;Skip this if No Divide clear 



A subroutine called by a JSR must have its entry point reserved for the PC 
word. Hence it is nonreentrant: the JSR modifies memory so the subroutine 
cannot be shared with other programs. The JSP requires an accumulator, 
but it is faster and is convenient for argument passing. To return from a 
JSR-called subroutine one usually addresses the PC word indirectly, return- 
ing to the location following the JSR. But there are two ways to get back 
from a JSP. We can address the PC word indhectly with a JRST @AC (or 
JRSTF @AC if the flags must be restored), but we can also get it by 
addressing AC as an index register: JRST (AC). By using the second return 
method we can place N words of data for the subroutine immediately after 
the call, and return to the location, following the data by giving a 
JRST A^(AC). 

Suppose we wish to call a print subroutine and supply the words from 
which the characters are to be taken. Our main program would contain the 
following: 

JSP T,PRINT ;Put PC word in accumulator T 

;Text inserted here by ASCIZ pseudo- 

', instruction, which automatically 

;places a zero (null) character at the 
;end 
;Next instruction here 

The subroutine can use T as a byte pointer which already addresses the first 
word of data. For the print routine, characters are loaded into another 
accumulator CH. 



79 



§2.9 
PRINT: 



HRLI T, 440700 
ILDB CH,T 
JUMPE CH,1(T) 



JRST PRINT+1 



PROGRAM CONTROL 

; Initialize left half of pointer 
•Increment pointer and load byte 
;Upon reaching zero character return 
;to one beyond last data word 
;Print routine 

;Get next character 



2-61 



JSA 



Jump and Save AC 



266 


A 


I 


X 


Y 



2.82 (2.93) JUS Interleaving memories saves 

.47 ( J6) MS. 



89 



12 13 14 



17 18 



35 



Place AC in location £", the effective address E iri AC left, and the contents 
of PC in AC right (at this time PC contains an address one greater than the 
location of the JSA instruction). Take the next instruction from location 
E+ 1 and continue sequential operation from there. The original contents 
of E are lost. 

While the processor is in user mode, if this instruction is executed as an in- 
terrupt instruction or in unrelocated 41 or 61 , bit 5 of the PC word stored is 
1 and the processor leaves user mode. 



JRA 



Jump and Restore AC 



2.92(3.14)^5 



267 


A 


I 


X 


1 



89 



12 13 14 



17 18 



35 



Place the contents of the location addressed by AC left into AC. Take the 
next instruction from location E and continue sequential operation from 
there. 



A JSA combines advantages of the JSR and JSP. JSA does modify 
^iiemory, but it saves PC in an accumulator without losing its previous 
contents (at a cost of not saving the flags). It is thus convenient for multiple- 
entry subroutines. In a subroutine called by a JSR, the returning JRST must 
refer to the (single) entry point. Since a JRA can retrieve the original PC by 
addressing AC as an index register, it is independent of any entry point 
without tying up an accumulator to the extent a JSP would. 

The accumulator contents saved by a JSA are restored by a JRA paired 
with it despite intervening JSA-JRA pairs. Hence these instructions are 
especially useful for nesting subroutines, as shown by this example. 



In Fortran IV, a CALL 
statement uses JSA with AC 
16. 



80 



2-62 



CENTRAL PROCESSOR 



JSA 



17, SI 



§2.9 



;Main program 

;Call to first subroutine (A) 



SI: 



First subroutine starts here 



JSA 17,S2 



;Can to second subroutine (B) 



JRA 17,(17) 

S2: 



; Return to ^ + 1 in main program 
; Second subroutine starts here 



JSA 



17,S3 



;Call to third subroutine (Q 



S3: 



JRA 17,(17) ; Return to 5 + 1 in first subroutine 

iThird subroutine starts here 



JRA 



17,(17) 



i Return to C+ 1 in second subroutine 



To call the next deeper subroutine at any level, a JSA places E and PC in the 
left and right of AC 17, saves the previous contents of AC 17 in £ (the first 
subroutine location), and jumps to £" + 1 . To return to the next higher level, 
a JRA restores the previous contents of AC 17 from#the location addressed 
by AC 1 7 left (the first subroutine location) and jumps to the location 
addressed by AC 1 7 right (the location following the JSA in the higher sub- 
routine). If N lines of data for the next subroutine follow a JSA, the return 
to the location following the data is made by giving a JRA 17,A^(17). 



Keeping instructions and the 
pushdown list in different 
memories saves .47 (.36) /is. 



PUSHJ 



Push Down and Jump 



3.00 (3.1 1) MS 



260 


A 


I 


X 


1 



89 



12 13 14 



17 18 



35 



Add 1 00000 1 8 to AC to increment both halves by one and place the result 
back in AC. If the addition causes the count in AC left to reach zero, set the 
Pushdown Overflow flag. Then place the current contents of the flags (as 
described above) in the left half of the location now addressed by AC right 
and the contents of PC in the right half of that location (at this time PC 
contains an address one greater than the location of the PUSHJ instruction). 
Take the next instruction from location E and continue sequential operation 
from there. 

The flags are unaffected except Byte Interrupt, which is cleared. The 
original contents of the location added to the list are lost. 

While the processor is in user mode, if this instruction is executed as an in- 
terrupt instruction or in unrelocated 41 or 61 , bit 5 of the PC word stored is 
1 and the processor leaves user mode. 



81 



§2,9 



PROGRAM CONTROL 



2-63 



POPJ 



Pop Up and Jump 



2.96 (3.18) MS 



263 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Subtract 1 00000 Ig from AC to decrement both halves by one and place the 
result back in AC. If the subtraction causes the count in AC left to reach - 1, 
set the Pushdown Overflow flag. Take the next instruction from the location 
addressed \>y the right half of the location that was addressed by AC right 
prior to the decrementing, and continue sequential operation from there. 



The effective address E is 
ignored. 



The address of the top item in the pushdown list is kept in the right half 
of the pointer in AC, and the program can keep a control count in the left 
half. The incrementing and decrementing of both halves of AC simulta- 
neously is effected by adding and subtracting 1 00000 Ig, Hence a count of 
-2 in AC left is increased to zero if 2*^ - 1 is incremented in AC right, and 
conversely, 1 in AC left is decreased to - 1 if zero is decremented in AC 
right. 

Since the pushdown list is independent of the subroutine called, PUSHJ- 
POPJ can be used like JSA-JRA for multiple entries. Moreover, ordering by 
level is inherent in the structure of a pushdown list [§2.2], so paired 
PUSHJ-POPJ instructions are excellent for nesting subroutines: there can be 
any number of subroutines at any level, each with more subroutines nested 
within it. Recursive subroutines are also possible. 

Unlike JSA-JRA, the pushdown, instructions tie up an accumulator, but 
the usual procedure is to keep both data and jump addresses in a single list so 
only one AC is required for the most complex pushdown operations. The 
programmer must keep track of whether a given entry in the list is data or 
a PC word; in other words, every item inserted by a PUSH should be 
removed by a POP, and every PUSH J should be matcjied by a POPJ. If flag 
restoration is desired, the returning 

POPJ P, 

can be replaced by 

POP P,AC 

JRSTF (AC) 

which requires another accumulator. If the flags are not important, data 
may be stored in the left halves of the PC words in the stack, reducing the 
required pushdown depth. 

By using the Pushdown Overflow flag and a control count in AC left, the 
programmer can set a limit to the size of the list by starting the count 
negative, or he can prevent the program from extracting more items than 
there are in the list by starting the count at zero, but he cannot do both at 
once. If only jump addresses are kept in the list, the first procedure limits 
the depth of nesting. A technique to catch extra POPJs is to put a PC word 
addressing an error routine at the bottom of the list. 



82 



2-64 



CENTRAL PROCESSOR 

2. 1 UNIMPLEMENTED OPERATIONS 



§2.10 



An unimplemented user oper- 
ation is usually referred to as 
a UUO, but this mnemonic 
means nothing to the assem- 
bler. UUOs are also some- 
times called "programmed 
operators'*. 



Many of the codes not assigned as specific instructions are executed as 
unimplemented user operations, wherein the word given as an instruction is 
trapped and must be interpreted by a routine included for this purpose by 
the programmer. In time sharing, however, half of the codes are set aside for 
user communication with the Monitor and are interpreted by it. Instructions 
that are illegal in user mode also trap in this manner. 



The total time required is 
that listed plus the time for 
the instruction in location 41 . 
Interleaving memories and 
I saves .47 (.36) fjis. 



"Execute" here means in the 
sense of the instruction XCT. 



Unimplemented User Operation 



2.33 (2.44) MS 



000-077 


A 


I 


X 


Y 



89 



12 13 14 



17 18 



35 



Store the instruction code, A and the effective address £ in bits 0-8, 9-12 
and 18-35 respectively of location 40; clear bits 13-17. Execute the 
instruction contained in location 41. The original contents of location 40 
are lost. 

All of these codes are equivalent when they occur in the Monitor or when 
time sharing is not in effect. But when a UUO appears in a user program, a 
code in the range 001-037 uses relocated locations 40 and 41 {ie 40 and 41 
in the user's block) and is thus entirely a part of and under control of the 
user program. A code in the range 040-077 on the other hand uses 
unrelocated 40 and 41, and the instruction in the latter location is under 
control of the Monitor; these codes are thus specifically for user communica- 
tion with the Monitor, which interprets them (refer to the Monitor manual 
for the meanings of the various codes). The code 000 executes in the same 
way as 040-077 but is not a standard communication code: it is included so 
that control returns to the Monitor should a user program wipe itself out. 

For a second processor connected to the same memory, the UUO trap is 
locations 140-141 instead of 40-41. 



The unimplemented operations also include the reserved (unassigned) 
instruction codes 100-127, which execute like the Monitor-calling UUOs 
but use unrelocated 60-61 (160-161 for a second processor); thus the 
Monitor steps in when a user gives an incorrect code. The codes 130-177, 
which are the floating point and byte manipulation instructions, are equiva- 
lent to the unassigned codes if unimplemented, ie if the optional hardware 
for them is not included. In this case all codes 100-177 trap to unrelocated 
60-6 1 . In general it is assumed that if software is available for floating point 
and byte manipulation, the Monitor is responsible for calling the appropriate 
routines- 



83 

§2.11 PROGRAMMING EXAMPLES 2-65 

2.11 PROGRAMMING EXAMPLES 

Before continuing to input-output and related subjects, let us consider som 
simple programs that demonstrate the use of a variety of the instruction 
described thus far. 

Suppose we wish to count the number of Is in a word. We could of 
course check every bit in the word. But there is a quicker way if we remem- 
ber that in any word and its twos complement the rightmost 1 is in the same 
position, both words are all Os to the right of this 1 , and no corresponding 
bits are the same to the left (the parts of both words at the left of the right- 
most 1 are complements). Hence using the negative of a word as a mask for 
the word in a test instruction selects only the rightmost I for modification. 
The example uses three accumulators: the word being tested (which is lost) 
is in T, the count is kept in CNT, and the mask created in each step is stored 
in TEMP. 

MOVEI CNT,0 ;ClearCNT 

MOVN TEMP,T ;Make mask to select rightmost 1 

TDZE T,TEM? ;Clear rightmost 1 in T 

AOJA CNT, .-2 ; Increase count and jump back 

;Skip to here if no Is left in T 

CNT is increased by one every time a 1 is deleted from T. After all Is have 
been removed, the TDZE skips. 

In the standard algorithm for converting a number A^ to its equivalent in 
base 6, one performs the series of divisions 



Njb 


= qi+rjb 


r,<b 


qjb 


= q2 + r2lb 


r2<b 


Q2/b 


= ^3 + r^lb 


r^<b 



qn-xlb = 0-¥rJb r„<b 

The number in base b is then r„. . .rjr2ri. Eg the octal equivalent of 61 
decimal is 75: 

61/8 = 7 + 5/8 

7/8 = + 7/8 

The following decimal print routine converts a 36-bit positive integer in 
accumulator T to decimal and types it out. The contents of T and T+ 1 are 
destroyed. The routine is called by a PUSH J P, DECPNT where P is the 
pushdown pointer. 



DECPNT: IDIVI T,12 

PUSH P,T+1 

SKIPE T 

PUSH J P, DECPNT 



128-10io 
Save remainder 
All digits formed? 
No, compute next one 



84 

2-66 CENTRAL PROCESSOR §2.11 

DECPNl: POP P,T ; Yes, take out in opposite order 

ADDI T,60 ;Convert to ASCII (60 is code for 0) 

JRST TTYOUT ;Type out 

This routine repeats the division until it produces a zero quotient. Hence it 
suppresses leading zeros, but since it is executed at least once it outputs one 
"0" if the number is zero. The TTYOUT routine returns with a POPJ P, to 
DECPNl until all digits are typed, then to the calling program. 

Space can be saved in the pushdown stack by storing the computed digits 
in the left halves of the locations that contain the jump addresses. This is 
accomplished in the decimal print routine by making the following substi- 
tutions. 

PUSH P,T+1 ^ HRLM T+1,(P) 
POP P,T -> HLRZ T,(P) 

The routine can handle a 36-bit unsigned integer if the IDIVI T, 1 2 is 
\ replaced by 

Macro interprets a number LSHC T,-tD35 ;Shift right 35 bits into T+1 

foUowing ID as decimal. LSH T+ 1 ,- 1 ; Vacate the T+ 1 sign bit 

DI VI T, 1 2 ;Divide double length integer by 1 

Many data processing situations involve searching for information in tables 

and lists of all kinds. Suppose we wish to find a particular item in a table 

beginning at location TAB and containing N items. Accumulator T contains 

the item. The right half of A is used to index through the table, while the 

- left half keeps a control count to signal when a search is unsuccessful. 



MOVSI 


A,-A^ 


;Put -N, in A 


CAMN 


T,TAB(A) 


;Skip if current item not the one 


JRST 


FOUND 


;Item found 


AOBJN 


A,.-2 


;Try next item until left count = 
;Item not in list 



HRLZI 


A,-iV 


CAME 


T,TAB(A) 


AOBJN 


A,.-l 


JUMPL 


A, FOUND 



The location of the item (if found) is indicated by the number in the right 
half of A (its address is that quantity plus TAB). A slightly different pro- 
cedure would be 



; Skip if current item is the one 

; Jump if left count < 
. . . ;Item not found 

Locations used for a list can be scattered throughout memory if data is 
kept in the left half of each location and the right half addresses the next 
location in the Hst. The final location is indicated by a zero right half. The 
following routine finds the last half word item in the list. It is entered at 
FIND with the first location in the list addressed by the right half of 
accumulator T. At the end the final item is in T right. 



85 



§2.11 



PROGRAMMING EXAMPLES 



2-67 



FIND: 



MOVE 


T,(T) 


TRNE 


T,777777 


JRST ' 


-2 


HLRZS 


T 


ig counts 


the length c 


MOVEI 


CNT,0 


JUMPE 


T,OUT 


HRRZ 


T,(T) 


AOJA 


CNT, -2 



;Move next item to T 
;Skipif ACright = 

;Move final item to right 



;Clear CNT 

;Jump out if T contains 
;Get next address 
;Count and go back 



Double Precision Floating Point. The following are straightforward rou- 
tines for handling double precision floating point arithmetic [§2.6 describes 
the floating point instructions ] . 



DFAD: 



UFA 

FADE 

UFA 

FADE 

POPJ 



A+1,M+1 

A,M 

A+l,A+2 

A,A+2 

P, 



DFSB: 



DFMP: 



DFN A,A+1 

PUSH J P,DFAD 

DFN A,A+1 

POPJ P, 

MOVEM A,A+2 



FMPR 

FMPR 

UFA 

FMPL 

UFA 

FADE 

POPJ 



A+2,M+1 

A+1,M 

A+l,A+2 

A,M 

A+l,A+2 

A,A+2 

P, 



;Sum of low parts to A+2 
;Sum of high parts to A, A+ 1 
;Add low part of high sum to A+2 
;Add low sum to high sum 



Negate double length operand 
Call double floating add 
-(M-AC) = AC-M 



Copy high AC operand in A+2 

One cross product to A+2 

Other to A+1 

Add cross products into A+2 

High product to A, A+ 1 

Add low part to cross sum in A+2 

Add low sum to high part of product 



A double precision division is of the form 



a_+ cxr^ 

b + C/X2-27 



Using the relationship 



A/b = q + rXl-'^Vb 



where q and r are the quotient and remainder produced by FDVE, the 
following rbutine computes a double length quotient by the algorithm 



- q + 



(r-qd)X2 



which gives a result correct to the next-to-last bit in the low order half. 



86 



2-68 



CENTRAL PROCESSOR 



§2.12 



DFDV: 



FDVL 


A,M 


MOVN 


A+2,A 


FMPR 


A+2,M+1 


UFA 


A+l,A+2 


FDVR 


A+2,M 


FADL 


A,A+2 


POPJ 


P, 



;Get high part of quotient 

;Copy negative of quotient in A+2 

; Multiply by low part of divisor 

;Add remainder ^ 

; Divide sum by high part of divisor 

;Add result to original quotient 



2.12 INPUT-OUTPUT 



A Times are given for 10 in- 
structions when they occur 
alone. When two 10 instruc- 
tions are given consecutively, 
the second often takes longer 
(refer to the timing chart in 
Appendix C for details). 



This is identical to UUO trap- 
ping [§2.10]. 



The input-output instructions govern all transfers of data to and from the 
peripheral equipment, and also perform many operations within the proc- 
essor. An instruction in the in-out class is designated by 1 1 1 in bits 0-2, ie 
its left octal digit is 7. Bits 3-9 address the device that is to respond to the 
instruction. The format thus allows for 1 28 codes, two of which, 000 and 
004 respectively, address the processor and priority interrupt, and are used 
for the console and time share hardware as well. A chart n Appendix A 
lists all devices for which codes have been assigned, and gives their 
mnemonics and DEC option numbers. 

Bits 13-35 are the same as in all other instructions: they are the /, X, and 
Y parts, which are used to calculate an effective address, set of conditions, 
or mask to be used in the execution of the instruction. The remaining bits, 
10-12, select one of the following eight 10 instructions. 

Note 

All instructions described in the remainder of this manual are in-out 
instructions, which cannot be executed in user programs unless the 
User In-out flag is set. If an in-out instruction appears in a user pro- 
gram while User In-out is clear, it does not perform the functions given 
for it in the instruction description. Instead it stores its own instruc- 
tion and device codes in bits 0-12 and its effective address E in bits 
18-35 of unrelocated location 40 (clearing bits 13-17), and then 
executes the instruction contained in location 4 1 , The latter location 
is under control of the Monitor [§2.15]. 

This user restriction will not be mentioned in the instruction descrip- 
tions, as it applies to all instructions from this point on. 



E will always be regarded as 
being bits 1 8-35, even though 
it is actually placed on both 
halves of the bus and many 
devices receive the informa- 
tion from the left half. 



CONO 



Conditions Out 



3.90 (4.01) /LIS 



7 


D 


20 


/ 


X 


Y 



23 



9 10 12 13 14 



17 18 



35 



Set Up device D with the effective initial conditions E. The number of con- 
dition bits in E that are actually used depends on the device. 















87 






§2.12 


' 


INPUT-OUTPUT 




2-69 


CONI 


Conditions In 




4.87 (4.98) MS 


Keeping instructions and op- 
erands in different memories 


7 


D 


24 


/ 


X 




Y 




saves .47 (.36) jus. Bringing 
conditions into fast memory 
saves .46 (.35) JUS. 


2 3 9 10 12 13 14 17 18 




35 



Read the input conditions from device D and store them in location E. The 
number of condition bits stored depends on the device; the remaining bits 
in location E are cleared. 



DATAO Data Out ' 



4.75 (4.97) jUs 



7 


D 


14 


/ 


X 


Y 



23 



9 10 12 13 14 



17 18 



Send the contents of location E to the data buffer in device D, and perform 
whatever control operations are appropriate to the device. 

The amount of data actually accepted by the device depends on the size 
of its buffer, its mode of operation, etc. The original contents of location E 
are unaffected. 



DATAI 


Data In 








4.87 (4.98) MS 


7 


D 


04 


/ 


X 


Y 



23 



9 10 12 13 14 



35 



Move the contents of the data buffer in device i) to location E, and perform 
whatever control operations are appropriate to the device. 

The number of data bits stored depends on the size of the device buffer, 
its mode of operation, etc. Bits in location E that do not receive data are 
cleared. 



Taking the output word from 
fast memory saves .34 jus. 



Keeping instructions and op- 
erands in different memories 
saves .47 (.36) jus. Placing the 
input data in fast memory 
saves .46 (.35) jus. 



CGNSZ -Conditions In and Skip if Zero 



23 



4.11 (4.22) JUS 



7 


D - 


30 


/ 


X 


Y 



9 10 12 13 14 



Test the input-conditions from device D against the effective mask E. If all 
condition bits selected by Is in £ are Os, skip the next instruction in 
sequence. 

If the device supplies more than 18 condition bits, only the right 18 are 
tested. 



2-70 



CENTRAL PROCESSOR 



§2.12 



CONSO 



23 



Conditions In and Skip if One 



4.11 (4.22) MS 



7 


D 


34 


1\ 


X 


1 



9 10 12 13 14 



35 



Test the input conditions from device<0 against the effective mask E. If any 
condition bit selected by a 1 in £ is 1 , skip the next instruction in sequence. 
If the device supplies more than IR condition bits, only the right 18 are 
tested. 



Keeping the pointer in fast 
memory saves .43 (.34) ^s. 



Keeping the pointer in fast 
memory saves .34 /is. Keeping 
the instruction and the data 
block in different memories 
saves .47 (.36))us. 



A block, 10 instruction is 
effectively a whole in-out 
data handling subroutine. It 
keeps track of the block loca- 
tion, transfers each data 
word, and determines when 
the block is finished. 

Initially the left half of the 
pointer contains the negative 
of the number of words in 
the block, the right half con- 
tains an address one less than 
that of the first word in the 
block. 



BLKO 



Block Out 



6.49 (6.71) MS 



7 


D 


10 


/ 


X 


Y 


23 

BLKI 


9 10 12 13 14 17 18 

Block In 




35 

6.49 (6.71) MS 


7 


D 


00 


/ 


X 


Y 



23 



9 10 12 13 14 



17 18 



35 



Add 1000001 8 to a pointer in location E to increment both halves by one, 
and place the result back in E. Then perform a data 10 instruction in the 
same direction as the block lO instruction, using the right half of the incre- 
mented pointer as the effective address. If the given instruction is a BLKO, 
perform a DATAO; if a BLKI, perform a DATAI. 

The remaining actions taken by this instruction depend on whether it is 
executed as a priority interrupt instruction [ §2.131 . 

♦ Not as an Interrupt Instruction. If the addition has caused the count in 
the left half of the pointer to reach zero, execute the next instruction in 
sequence. Otherwise skip the next instruction. 

♦ As an Interrupt Instruction. If the addition has caused the count in the 
left half of the pointer to reach zero, execute the instruction in the second 
interrupt location for the channel. Otherwise dismiss the interrupt and 
return to the interrupted program. 



The above eight instructions differ from one another in their total effect, 
but they are nbt all different with respect to any given device. A BLKO acts 
on a device in exactly the same way as a DATAO — the two differ only in 
counting and othfer operations carried out within the processor and memory. 
Similarly, no device can distinguish between a BLKI and a DATAI; and a 
device always suppUes the same input conditions during a CONI, CONSZ or 
CONSO whether the program tests them or simply stores them. 

Hence the eight instructions may be categorized as of four types, repre- 
sented by the first four instructions described above. Moreover, a complete 
treatment of the programming of any device can be given in terms of these 
four instructions, two of which are for input and two for output. The four 



89 



§2.12 



INPUT-OUTPUT 



2-71 



exhaust the types of information transfer that occur in the 10 system, at 
least three of which are applicable to any given device. Thus all instruction 
descriptions in the rest of this manual will be of the CONO, CONI, DATAO 
and DATAI instructions combined with the various device codes. The dis- 
cussion of each device will present timing information pertinent to device 
operation, but no instruction times will be included as they are identical to 
those given above. 

Every device requires initial conditions; these are sent by a CONO, which 
can supply up to eighteen bits of control information to the device control 
register. The program can determine the status of the device from up to 
thirty-six bits of input conditions that can be read by a CONI (but only the 
right eighteen can be tested by a CONSZ or CONSO). Some input bits 
simply reflect initial conditions sent by a previous CONO; others are set up 
by output conditions but are subject to subsequent adjustment by the 
device; and still others, such as status levels from a tape transport, have no 
direct connection with output conditions. 

Data is moved in and out in characters of various sizes or in full 36-bit 
words. Each transfer between memory and a device data buffer requires a 
single DATAI or DAT Ad. Every device has a CONO and CONI, but it may 
have only one data instruction unless it is capable of both input and output. 
Eg, the paper tape reader has only a DATAI, i\iQ tape punch has only a 
DATAO, but the teletype has both. (A high speed device, such as a disc file, 
can be connected to the DP 10 Data Channel, which in turn is connected 
directly to memory by a separate memory bus and handles data auto- 
matically. This eliminates the need for the program to give a DATAO or 
DATAI for each transfer.) 

A Typical lO Device. Every device has a 7-bit device selection network, a 
priority interrupt assignment, and at least two flags, Busy and Done, or some 
equivalent. The selection network decodes bits 3-9 of the instruction so 
that only the addressed device responds to signals sent by the processor over 
the in-out bus. To use the device with the priority interrupt, the program 
must assign a channel to it. Then whenever an appropriate event occurs in 
the device, it requests an interrupt on the assigned channel. 

The Busy and Done flags together denote the basic state of the device. 
When both are clear the device is idle. To place the device in operation, a 
CONO or DATAO sets Busy. If the device will be used for output, the pro- 
gram must give a DATAO that sends the first unit of data - a word or char- 
acter depending on how the device handles information. When the device has 
processed a unit of data, it clears Busy and sets Done to indicate that it is 
ready to receive new data for output, or that it has data ready for input. 
In the former case the program would respond with a DATAO to send more 
data; in the latter, with a DATAI to bring in the data that is ready. If an 
interrupt channel has been assigned to the device, the setting of Done signals 
the program by requesting an interrupt; otherwise the program must keep 
testing Done to determine when the device is ready. 

All devices function basically as described above even though the number 
of initial conditions varies considerably. Besides Busy and Done flags, the 
tape reader and punch have a Binary flag that determines the mode of 
operation of the device with respect to the data it processes - alphanumeric 



The word "input" used with- 
out qualification always refers 
to the transfer of data from 
the peripheral equipment into 
the processor; "output" refers 
to the transfer in the opposite 
direction. 



A DATAI that addresses an 
output-only device simply 
clears location E. DATAI PI, 
(code 70044) produces only 
this effect as the priority in- 
terrupt has no data for input. 
On the other hand a DATAO 
that addresses an input-only 
device is a no-op. 

When the device code is 
undefined or the addressed 
device is not in the system, 
a DATAO, CONO or CONSO 
is a no-op, a CONSZ is an 
absolute skip, a DATAI or 
CONI clears location E. 



Busy and Done both set is a 
meaningless situation. 



90 



2-72 



CENTRAL PROCESSOR 



§2.12 



Occasionally a device with a 
second code may use a 
DATAI or DATAO to trans- 
mit additional control or 
maintenance information. 



or, binary. The teletype has no binary flag, but it has two Busy flags and two 
Done flags — one pair for input, another for output. A complicated device, 
such as magnetic tape, may require two device codes to handle the large 
number of conditions associated with it. Initial conditions for a tape system 
include a transport address and an actual command the tape vcontrol is to 
perform; input conditions include error flags and transport status levels. 

Most 10 devices involve motion of some sort, usually mechanical (in a 
display only the electron beam moves). With respect to mechanical motion 
there are two types of devices, those that stay in motion and those that do 
not. Magnetic tape is an example of the former type. Here the device 
executes a command (such as read, write, space forward) and the done flag 
indicates when the entire operation is finished. A separate data flag signals 
each time the device is ready for the program to give a DATAI or DATAO, 
but the tape keeps moving until an entire record or file has been processed. 

Paper tape, on the other hand, stops after each transfer, but the program 
need not give a new CONO every time; The reader logic is set up so that a 
DATAI not only reads the data, but also clears 'Done and sets Busy. Hence 
if the instruction is given within a critical time, the tape moves continuously 
and only two CONO s are required for a whole series of transfers: one to start 
the tape, and one to stop it after the final DATAI. 

Other devices operate in one or the other of these two ways but differ in 
various respects. The tape punch and teletype output are like the reader. 
Teletype input is initiated by^ the operator striking a key rather than by the 
program. The card reader reads an entire card on a single CONO, with a 
DATAI required for each column. The DECtape ^ays in motion, and the 
program must givp a CONO to stop it or it will go all the way to the end 
zone. 



Readin Mode 



This nJiode of processor operation provides a means of placing information 
in memory without relying on a program already in memory or loading one 
word at a time manually. Its principal use is to read in a short loader 
program which is then used for loading other information. A loader program 
should ordinarily be Used rather than readin mode, as a loader can check the 
validity of the information read. 

Pressing the readin key on the console activates readin mode by starting 
the processor in a special hardware sequence that simulates a DATAI fol- 
lowed by a series of BLKI instructions, all of which address the device whose 
code is selected by the readin device switches on the small panel at the left 
of the paper tape reader. Various devices can be used, and for each there 
are special rules that must be followed. But the readin mode characteristics 
of any particular device are treated in the discussion of the device. Here we 
are concerned only with the general characteristics. 

The information read is a block of data (such as a loader program) pre- 
ceded by a pointer for the BLKI instructions. The left half of the pointer 
contains the negative of the number of words in the block, the right half 
contains an address one less than that of the location that is to receive the 
first word. 



§2.13 



91 

PRIORITY INTERRUPT 



2-73 



To read in, the operator must set up the device he is using, set its code 
into the readin device switches, and press the readin key. The processor 
places the device in operation, brings the first word (the pointer) into 
location 0, and then reads the data block, placing the words in the locations 
specified by the pointer. Data can be placed anywhere in memory (including 
fast memory) except in location 0. The operation affects none of memory 
except location and the block area. 

Upon completing the block, the processor halts only if the single instruc- 
tion switch is on. Otherwise it leaves readin mode, and begins normal 
operation by executing the last word in the block as an instruction. 



Console Data Transfers 

Neither the processor nor the priority interrupt system require all four types 
of lO instructions, so the program can make use of their device codes for 
communicating with the console. 



DATAI APR, 



Data In. Console 



70004 



: 



12 13 14 17 18 

Read the contents of the console data switches into location E. 



35 



Macro also recognizes the 
mnemonic RSW (Read 
Switches) as equivalent to 
DATAI APR,. 



DATAO PI, 



Data Out, Console 



70054 


/ 


X 


Y 



12 13 14 



17 18 



35 



Unless the console MI program disable switch is on, display the contents of 
location Em the console memory indicators and turn on the triangular light 
beside the words PROGRAM DATA just above the indicators (turn off the 
Ught beside MEMORY DATA). 

Once the indicators have been loaded by the program, no address condi- 
tion selected from the console [§2.16] can load them until the operator 
turns on the MI program disable switch, executes a key function that ref- 
erences memory, or presses the reset key. 



2.13 PRIORITY INTERRUPT 



Most in-out devices must be serviced infrequently relative to the processor 
speed and only a small amount of processor time is required to service them, 
but they must be serviced within a short time after they request it. Failure 
to service within the specified time (which varies among devices) can often 



92 

2-74 CENTRAL PROCESSOR §2.13 

result in loss of information and certainly results in operating the device 
below its' maximum speed. The priority interrupt is designed with these 
considerations in mind, ie the use of interruptions in the current program 
sequence facilitates concurrent operation of the main program and a number 
of peripheral devices. The hardware also allows conditions internal to the 
processor to signal the program by requesting an interrupt. 

Interrupt requests are handled through seven channels arranged in a 
priority chain, with assignment of devices to channels entirely at the discre- 
tion of the programmer. To assign a device to a channel, the program sends 
the number of the channel to the device control register as part of the condi- 
tions given by a CONO (usually bits 33--35), Channels are numbered 1-7, 
with 1 having the highest priority; a zero assignment disconnects the device 
from the interrupt channels altogether. Any number of devices can be 
connected to a single channel, and some can be connected to two channels 
(eg a device may signal that data is ready on one channel, that an error has 
occurred on another). 

Interrupt Requests. When a device requires service it sends an interrupt 
request signal over the in-out bus to its assigned channel in the processor. If 
the channel is on, the processor accepts the request at the next memory 
access unless the processor is either starting an interrupt on any channel or 
holding an interrupt on the same channel. The request signal is a level, so 
it remains on the bus until turned off by the program (CONO, DATAO or 
* DATAI). Thus if a request is not accepted because of the conditions given 
above, it will be accepted when those conditions no longer hold. A single 
channel will shut out all others of lower priority if every time its service 
routine dismisses the interrupt, a device assigned to it is already waiting with 
another request. The program can usually trigger a request from a device but 
delay its acceptance by turning on the channel later. 

Starting an Interrupt. After a request is accepted the channel must wait 
for the interrupt to start. No interrupts can be started unless the priority 
interrupt system is active. Furthermore, the processor cannot start an 
interrupt if it is already* holding an interrupt on a channel with priority 
higher than those on which requests have been accepted (in other words if 
the current program is a higher priority interrupt routine). If there is a 
higher priority channel waiting, the processor stops the current program to 
start an interrupt on the waiting channel that has highest priority. The inter- 
rupt starts following the retrieval of an instruction, following the retrieval of 
an address word in an effective address calculation (including the second cal- 
culation using the pointer in a byte instruction), or following a transfer in a 
BLT. When an interrupt starts, PC points to the interrupted instruction, so 
that a correct return can later be made to the interrupted program. 

Two memory locations are assigned to each channel: unrelocated locations 
Interrupt locations for a sec- 40 + 2A^ and 41 + 2N, where N is the channel number. Channel 1 uses loca- 
ond processor are 140 + 2N tions 42 and 43, channel 2 uses 44 and 45, and so on to channel 7 which 
and 141 + 2N. ^^gg 55 ^j^^j 57 jyic processor starts an interrupt on channel A^ by executing 

the instruction in location 40 + 2A^. 

An instruction executed by the interrupt hardware in response to an 
interrupt request is referred to elsewhere in this manual as being executed 
"as an interrupt instructioli". Some instructions, when so executed, perform 



93 

§2.13 PRIORITY INTERRUPT . 2-75 

different functions than they do when executed in other circumstances. And 
the difference is not due merely to being executed in an interrupt location or 
in response (by the program) to an interrupt. To be an interrupt instruction, 
an instruction must be executed by the interrupt hardware, in location 
40+ 2A^ or 41 + 2A^, because of a request on channel N. §2.12 describes 
the two ways a BLKO is performed. If a BLKO is contained in an interrupt 
routine called by a JSR, it is not executed "as an interrupt instruction" even 
if the routine is stored within the interrupt locations. There are two 
categories of interrupt instructions. 

♦ Non-IO Instructions. 'After executing a non-IO interrupt instruction, the 
processor holds an interrupt on the channel and returns control to PC. Hence 
the instruction is usually a jump to a service routine. If the processor is in 
user mode and the interrupt instruction is a JSR, JSP, PUSHJ, JSA or JRST, 
the processor leaves user mode (the Monitor thus handles all interrupt rou- " 
tines [§2.151). 

If the interrupt instruction is not a jump, the processor continues the 
interrupted program while holding an interrupt - in other words it now 
treats the interrupted program as an interrupt routine. Eg the instruction 
might just move a word to a particular location. Such procedures are 
usually reserved for maintainence routines or very sophisticated programs. 

♦ Block or Data 10 Instructions. One or the other of two actions can result 
from executing one of these as an interrupt instruction. 

If the instruction in 40 + 2A^ is a BLKI or BLKO and the block is not 
finished {ie the count does not cause the left half of the pointer to reach 
zero), the processor holds and immediately dismisses an interrupt on the 
channel, and returns to the interrupted program. The same action results 
if the instruction is a DATAI or DATAO. 

If the instruction in 40 + 2N is a BLKI or BLKO and the count does reach 
zero, the processor continues to start the interrupt by executing the 
instruction in location 41 + 2A^. This cannot be an 10 instruction and the 
actions that result from its execution as an interrupt instruction are those 
given above for non-IO instructions. 

Caution 

The execution, as an interrupt instruction, of a 
CONO, CONI, CONSO or CONSZ in location 
40 + 2A^ or any lO instruction in location 41 + 2A^ 
hangs up the processor. 

Dismissing an Interrupt. Automatic dismissal of an interrupt occurs only 
in a DATAI or DATAO, or in a BLKI or BLKO with an incomplete block. 
Following any non-IO interrupt instruction, the processor holds an interrupt 
until the program dismisses it, even if the interrupt routine is itself inter- 
rupted by a higher priority channel. Thus interrupts can be held on a num- 
ber of channels simultaneously, but from the time an interrupt is started 
until it is dismissed, no interrupt can be started on that channel or any 
channel of lower priority (requests, however, can be accepted on lower 
priority channels). 



2-76 



94 



CENTRAL PROCESSOR 



§2.13 



A routine dismisses the interrupt by using a JEN (JRST 12,) to return to 
the interrupted program (the interrupt system must be active when the JEN 
is given). This instruction restores the channel on which the interrupt is 
being held, so it can again accept requests, and interrupts can be started on 
it and lower priority channels. JEN also restores the flags, whose states were 
saved in the left half of the PC word if the routine was called by a JSR, 
JSP, or PUSHJ [§2.9] . If flag restoration is not deshed, a JRST 10, can 
be used instead. 

Caution 

An interrupt routine must dismiss the interrupt 
when it returns to the interrupted program, or its 
channel and all channels of lower priority, will be 
disabled, and the processor will treat the new 
program as a continuation of the interrupt routine. 

Priority Interrupt Conditions. The program can control the priority in- 
terrupt system by means of condition lO instructions. The device code is 
004, mnemonic PL 



CONO PI. 



Conditions Out, Priority Interrupt 



70060 


/ 


X 


Y 



12 13 14 17 18 



35 



Perform the functions specified by E as shown (a 1 in a bit produces the 
indicated function, a has no effect). 













INITIATE 
INTERRUPT 

I 


DEACTIVATE ACTIVATE 
PI PI 




CLEAR 

POWER 

FAILURE 

FLAG 


CLEAR 
PARITY 
ERROR 
FLAG 


disable] ENABLE 

PARITY ERROR 

INTERRUPT 

1 




CLEAR 

PI 
SYSTEM 


i j TURN 1 TURN 
' ' ON ' OFF 

SELECTED CHANNELS 
1 1 


\ 


/ 


SELECT CHANNELS FOR BITS 24, 25, 26 
1 2 1 3 1 4 5 1 6 1 


7 


18 


19 


20 ' 21 


22 


23 


24 25 26 


27 


28 


29 30 3t 32 33 34 


35 



Bits 18-21 are actually for 
processor conditions [§2.14], 



Notes. 
20 

21 

23 

24 



Prevent the setting of the Parity Error flag from requesting an 
interrupt on the channel assigned to the processor. 

Enable the setting of the Parity Error flag to request an interrupt 
on the channel assigned to the processor. 

Deactivate the priority interrupt system, turn off all channels, 
eliminate all interrupt requests that have already been accepted but 
are still waiting, and dismiss all interrupts that are currently being 
held.. 

Request interrupts on channels selected by Is in bits 29-35, and 
force the processor to accept them even on channels that are off. 



95 



§2.13 



PRIORITY INTERRUPT 



2-77 



A request is lost if it is made by this means to a channel on which 
an interrupt is already being held. 

25 Turn on the channels selected by Is in bits 29-35 so interrupt 
requests can be accepted on them. 

26 Turn off the channels selected by Is in bits 29-35, so interrupt 
requests cannot be accepted on them unless made by a CONO PI, 
with a 1 in bit 24. 

27 Deactivate the priority interrupt system. The processor can then still 
accept requests, but it can neither start nor dismiss an interrupt, 

28 Activate the priority interrupt system so the processor can accept 
requests and can start, hold and dismiss interrupts. 



CONI PI, 



Conditions In, Priority Interrupt 



70064 


/ 


X 


Y 



12 13 14 



17 18 



35 



Read the status of the priority interrupt (and several bits of processor condi- 
tions) into the right half of location E as shown. 







PARITY ERROR , 
INTERRUPT 
ENABLED 
/ 














POWER 
FAILURE 


PARITY 
ERROR 


/ 


INTERRUPT IN PROGRESS ON CHANNELS 
1 1 2 1 3 1 4 1 5 1 6 '7 


PI 
ACTIVE 


1 


2 


CHANNELS ON 
3 1 4 5 


6 


7 


18 


19 


20 


21 22 23 ^ 24 25 26 27 


28 


29 


30 


31 32 33 


34 


35 



Notes. 

18 Ac power has failed. The program should save PC, the flags and fast 
memory in core, and halt the processor. 

The setting of this flag requests an interrupt on the channel 
assigned to the processor. If the flag, remains set for 5 ms, the 
processor is cleared. 

19 A word with even parity has been read from core memory. If bit 20 
is set, the setting of the Parity Error flag requests an interrupt on the 
channel assigned to the processor. 

28 The priority interrupt system is active. 

Channels that are on are indicated by Is in bits 29-35; Is in bits 21-27 
indicate channels on which interrupts are currently being held. 



Note that bits 18-20,actually 
read processor status condi- 
tions [§2.14] . 



Timing. The time a device must wait for an interrupt to start depends on 
the number of channels in use, and how long the service routines are for 
devices on higher priority channels. If only one device is using interrupts. 



96 

2-78 .' CENTRAL PROCESSOR . §2.14 

it need never wait longer than the time required for the processor to finish 
the instruction that is being performed when the request is made. The 
maximum time can be considered to be about 1 5 jus for FDVL, but a ridicu- 
lously long shift could take over 35 /is. 

Special Considerations. On a return to an interrupted program, the proc- 
essor always starts the interrupted instruction over from the beginning. This 
causes special problems in a BLT and in byte manipulation. 

An interrupt can' start following any transfer in a BLT. When one does, 
the BLT puts the pointer (which has counted off the number of transfers 
already made) back in AC. Then when the instruction is restarted following 
the interrupt, it actually starts with the next transfer. This means that if 
interrupts are in use, the programmer cannot use the accumulator that holds 
the pointer as an index register in the same BLT, he cannot have the BLT 
load AC except by the final transfer, and he cannot expect AC to be the 
same after the instruction as it was before. 

An interrupt can also start in the second effective address calculation in a 
two-part byte instruction. When this happens, Byte Interrupt is set. This 
flag is saved as bit 4 of a PC word, and if it is restored by the interrupt 
routine when the interrupt is dismissed, it prevents a restarted ILDB or 
IDPB from incrementing the pointer a second time. This means that the 
interrupt routine must check the flag before using the same pointer, as it 
now points to the next byte. Giving an ILDB or IDPB would skip a byte. 
And if the routine restores the flag, the interrupted ILDB or IDPB would 
process the same byte the routine did. 

Programming Suggestions. The Monitor handles all interrupts for user 
programs. Even if th6 User In-out flag is set, a user program generally cannof 
reference the interrupt locations to set them up. Procedures for informing 
the Monitor of the interrupt requirements of a user program are discussed in 
the Monitor manual. ^ - 

For those who do program priority interrupt routines, there are several 
rules to remember. 

♦ No requests can be accepted, not Qven on higher priority channels, while 
a break is starting. Therefore do not use lengthy effective address calcula- 
tions in interrupt instructions. 

♦ The interrupt instruction that calls the routine must save PC if there is to 
be a return to the interrupted program. Generally a JSR is used as it saves 
both PC and the flags, and it uses no accumulator. 

♦ The principal function of an interrupt routine is to respond to the situa- 
tion that caused the interrupt. Eg computations that can be performed 
outside the routine should not be included within it. 

♦ The routine must disniiss the interrupt (with a JEN) when returning to the 
interrupted program. The flags should be restored. 



2.14 PROCESSOR CONDITIONS 



There are a number of internal conditions that can signal the program by 
requesting an interrupt on a channel assigned to the processor. Flags for 



97 



§2.14 



PROCESSOR CONDITIONS 



2-79 



power failure and parity error are handled by the condition 10 instructions 
that address the priority interrupt system [ §2.13] . The remaining flags are 
handled b'y conditioj> instructions that address the processor. Its device code 
is 000, mnemonic APR or CPA. 



CONO APR, 



Conditions Out, Arithmetic Processor 



70020 


/ 


X 


Y 



12 13 14 



17 18 



35 



Perform the functions specified by E as shown (a 1 in a bit produces the 
indicated function, a has no effect). 



CLEAR 

PUSHDOWN 

OVERFLOW 

1 




CLEAR 
MEMORY 
PROTECTION 
FLAG^ 


CLEAR 

NONEXISTENT 
MEMORY FLAG 

/ 






CLEAR 

FLOATING 

OVERFLOW 


CLEAR 
OVERFLOW 

1 


1 


CLEAR 

ALL 
IN-OUT 
DEVICES 




CLEAR 

ADDRESS 

BREAK 

FLAG 


\ 


V 


disable] ENABLE 

CLOCK 
INTERRUPT 

t 


CLEAR 
CLOCK 
FLAG 


disable! ENABLE 
INTERRUPT 




oisable| enable 
overflow 

INTERRUPT 

1 




. PRIORITY 
INTERRUPT 
ASSIGNMENT 
1 1 


18 


19 


20 


21 


22 


23 


24 25 


26 


27 28 


29 


30 31 


32 


33 34 35 



Notes. 

Enabling a particular flag to interrupt means that henceforth the setting 
of the flag will request an interrupt on the channel assigned (by bits 33-35) 
to the processor. Disabling prevents the flag from triggering a request. 

A 1 in bit 19 produces the 10 reset signal, which clears the control logic in 
all of the peripheral equipment (but affects neither the priority interrupt sys- 
tem, nor the processor flags cleared by this instruction or CONO PI,). 



CONI APR, 



Conditions In, Arithmetic Processor 



70024 


/ 


X 


y 



12 13 14 



17 18 



35 



Read the status of the processor into the right half of location E as shown 
(all interrupt requests are made on the channel assigned to the processor). 



PUSHDOWN 
OVERFLOW 



MEMORY 

PROTECTION 

FLAG 



NONEXISTENT 
MEMORY 



CLOCK 

INTERRUPT 

ENABLED 



FLOATING 
OVERFLOW 
INTERRUPT 
ENABLED 



FLOATING 
OVERFLOW 



OVERFLOW 
INTERRUPT 
ENABLED 



OVERFLOW 



USER 
IN-OUT 



ADDRESS 
BREAK 



CLOCK 
FLAG 



TRAP 
OFFSET 



PRIORITY 

INTERRUPT 

ASSIGNMENT 

_J L_ 



20 



22 



23 



24 



25 



26 



27 



28 



29 



30 



33 



34 



35 



MAY 1968 



98 



2-80 



CENTRAL PROCESSOR 



§2.14 



Notes. 
19 



PC bears no relation to the 
break if the access was re- 
quested for a console key 
fiinction. 



This flag can also be set by 
an instruction executed from 
the console while tHe USER 
MODE light is on, in which 
case PC bears no relation to 
the violation. 

PC bears no relation to the , 
unanswered reference if the 
attempted access originated 
from a console key function. 



A 20 



21 



A 22 



23 



26 



29 



30 

32 



Pushdown Overflow - in a PUSH or PUSH J the count in AC left 
reached zero; or in a POP or POPJ the count reached -1. The setting 
of this flag requests an interrupt. 

User In-out - even if the processor is in user mode, no instructions 
are illegal (but protection and relocation still apply) [ § 2.1 5 ] . 

Address Break - while the console address break switch was on, the 
processor requested access to the memory location specified by the 
address switches and the memory reference was for the purpose 
selected by the address condition switches as follows: 

The instruction switch was on and access was for retrieval of an 
instruction (including an instruction executed by an XCT or con- 
tained in an interrupt location or a trap for an unimplemented 
operation) or an address word in an effective address calculation. 

The data fetch switch was on and access was for retrieval of an 
operand (other than in an XCT). 

The write switch was on and access was for writing a word in 
memory. 

The setting of this flag requests an interrupt, at which time PC points 
to the instruction that was being executed or to the one following it. 
Memory Protection - a user program attempted to access a memory 
location outside of its area or to write in a write-protected part of its 
area and the user instruction was terminated at that time. The setting 
of this flag requests an interrupt, at which time PC points either to 
the instruction that caused the violation or to the one following it. 
Nonexistent Memory - the processor attempted to access a memory 
that did not respond within 100 iis. The setting of this flag requests 
an interrupt, at which time PC points either to the instruction con- 
taining the unanswered reference or to the one following it. 
Clock — tiiio flag is set at the ac power line frequency and can thus 
be used for low resolution timing (the clock has high long term 
accuracy). If bit 25 is set, the settmg Of the Clock flag requests an 
interrupt. 

Floating Overflow - this is one of the flags saved in a PC word, and 
the conditions that set it are given at the beginning of §2.9. If bit 28 
is set, the setting of Floating Overflow tequests an interrupt, at which 
time PC points to the instruction following that in which the over- 
flow occurred. 

Trap Offset - the processor is using locations 140-161 for unimple- 
mented operation traps and interrupt locations. 

Overflow - this is one of the flags saved in a PC word, and the condi- 
tions that set it are given at the beginning of §2.9. If bit 31 is set, 
the setting of Overflow requests an interrupt, at which time PC 
pomts to the instruction following that in which the overflow 
occurred. 



99 

§2.15 TIME SHARING 2-8 1 

2.15 TIME SHARING 

Without time sharing the system has a single user and the program has no 
restrictions except those inherent in the hardware: the programmer must 
stay within the memory capacity, observe the restrictions placed on the use 
of certain memory locations by the hardware [§13], and observe the 
restrictions on interrupt instructions. Optional hardware can restrict proc- 
essor operation to permit time sharing by a number of programs. Each user 
program is run with the processor in user mode, in w^hich th^ program must 
operate within an assigned area in core and certain operations may be illegal. 
A program that runs unrestricted - the Monitor - is responsible for 
scheduling user programs, servicing interrupts, handling input-output needs, 
and taking action when control is returned to it from a user progr^tn. 

Every user is assigned a core area and the rest of core is protected from 
him — he cannot gain access to the protected area for either storage or 
retrieval of information. The assigned area is divided into two parts. The 
low part is unique to a given user and can be used for any purpose. The 
high part may be for a single user, or it may be shared by several users. The 
Monitor can write-protect the high part so that the user cannot alter its 
contents, ie he cannot write anything in it. The Monitor would do this when 
the high part is to be a pure procedure to be used reentrantly by several 
users. One high pure segment may be used with any number of low impure 
segments. The user can request that the Monitor write-protect the high part 
of a single program, eg in order to debug a reentrant program. All users write 
programs beginning at address for the low part, and beginning usually at 
400000 for the high part. The programmed addresses are retained in the 
object program but are relocated by the hardware to the physical area 
assigned to the user as each access is made while the program is running. 

The size and position of the user area are defined by specifying protection 
and relocation addresses for the low and high blocks. The protection address 
determines the maximum address the user can give; any address larger than 
the maximum is illegal. The relocation address is the address, as seen by the 
Monitor and the hardware, of the first location in the block. The Monitor 
defines these addresses by loading four 8-bit registers, each of which 
corresponds to the left eight bits (18-25) of an address whose right ten bits 
are all 0. 

To determine whether an address is legal its left eight bits are compared 
with the appropriate protection register, so the maximum user address 
consists of the register contents in its left eight bits, 1777 in its right ten bits 
(ie it is equal to the protection address plus Mil). Since the set of all 
addresses begins at zero, a block is always an integral multiple of 1024io 
(20003) locations. Relocation is accomplished simply by adding the contents 
of the appropriate relocation register to the user address, so the first address 
in a block is a multiple of 2000. The relative user and relocated address 
configurations are therefore as illustrated here, where /*/,/?/, Ph and Rh are 
respectively the protection and relocation addresses for the low and high 
parts as derived from the 8-bit registers loaded by the Monitor. If the low 
part is larger than 128K locations, ie more than half the maximum memory 
capacity (P/ > 400000), the high part starts at the first location after the low 



2-82 

Note that the relocated low 
part is actually in two sections 
with the larger beginning at 
Ri + 20. This is because ad- 
dresses 0-17 are not relo- 
cated, all users having access 
to the accumulators. The 
Monitor uses the first sixteen 
locations in the low user 
block to store the user's accu- 
mulators when his program is 
not running. 

Some systems have only the 
low pair of protection and 
relocation registers. In this 
case the user program is 
always nonreentrant and the 
assigned area comprises only 
the low part. 



The user can actually write 
any size program: the Monitor 
will assign enough core for his 
needs. Basically the user must 
write a sensible program; if he 
uses absolute addresses scat- 
tered all over memory his 
program cannot be run on a 
time shared basis with others. 



These instructions are illegal 
unless User In-out is set. 



100 

CENTRAL PROCESSOR 




§2.15 



Pi+ Mil 



400000 



P^+ 1777 



777777 



LOW 



ILLEGAL 



HIGH 



ILLEGAL 







r 
\ 
\ ' 

\ 
\ 






HIGH 


/ \/ \ 

/ A \ 

/ / ^ ^ - 


/ / \ ^ 
/ / ^ 
/ / \ 

' i \ 
/ \ 

/ 
/ 




LOW 





NON- 
EXISTENT I 
MEMORY 



17 
/?ft + 400000 

/?ft+P;,+ 1777 

^'/?, + 20 



Rfi MUST BE NEGATIVE 
UNLESS SYSTEM HAS A 
MEMORY LARGER THAN 
128K 



USER ADDRESSES 
BEFORE RELOCATION 



TYPICAL PHYSICAL ADDRESS 
CONFIGURATION AFTER RELOCATION 



part (at location Pi + 2000). The high part is hmited to 1 28K. If the Monitor 
defines two parts but does not write-protect the high part, the user has a 
two-part nonreentrant program. 

If the user attempts to access a location outside of his assigned area, or 
if the high part is write-protected and he attempts to alter its contents, the 
current instruction terminates immediately, the Memory Protection flag is 
set (status bit 22 read by CONI APR,), and an interrupt is requested on the 
channel assigned to the processor [ §2.14] . 

User Programming. The user must observe the following rules when pro- 
gramming on a time shared basis. {Refer to the Monitor manual for further 
information including use of the Monitor for input-output. ] 

♦ Use addresses only within the assigned blocks for all purposes - retrieval 
of instructions, retrieval of addresses, storage or retrieval of operands. The 
low part contains locations with addresses from to the maximum; the high 
part contains from the greater of 400000 or Pi + 2000 to the maximum. 
Either part can address the other. 

♦ If the high part is write-protected, do not attempt to store anything in it. 
In particular do not execute a JSR or JSA into the high part. . 

♦ Use instruction codes 000 and 040-127 only in the manner prescribed in 
the Monitor manual. 

♦ Unless User In-out is set do not give any 10 instruction, HALT (JRST 4,) 
orJEN(JRST 12, (specifically JRST 10,)). The program can determine if 
User In-out is set by examining bit 6 of the PC word stored by JSR, JSP or 



101 



§2.15 



TIME SHARING 



2^83 



PUSHJ. 

The user can give a JRSTF (JRST 2,) but a in bit 5 of the PC word does 
not clear User (a program cannot leave user mode this way); and a 1 in bit 6 
does not set User In-out, so the user cannot void any of the restrictions 
himself. Note that a in bit 6 will clear User In-out, so a user can discard 
his own special privileges. 

UUOs 001-037 execute normally and are relocated to addresses 40 and 
41 in the low block [§2.10]. 

Monitor Programming. The Monitor must assign the core area for each 
user program, set up trap and interrupt locations, specify whether the user 
can give 10 instructions, transfer control to the user program, and respond 
appropriately when an interrupt occurs or an instruction is executed in 
unrelocated 41 or 61. 

Core assignment is made by this instruction. 



OATAO APR, Data Out, Arithmetic Processor 



70014 


/ 


X 


Y 



12 13 14 17 18 



35 



Load the protection and relocation registers from the contents of location 
E as shown, where Pi, P^, Rj and R^ are the protection and relocation 



^/l8-25 
-l_J |_J I— 



p 

^18-; 



7 8 9 



^-, 



8-25 



J L 



16 17 18 



25 26 27 



34 35 



addresses defined above. If write-protect bit P (bit 17) is 1 , do not allow the 
user to write in the high part of his area. 



For a two part nonreentrant 
program, set P = 0. For a one- 
part nonreentrant program, 
make P^ < /•;. If the hardware 
has only one set of protection 
and relocation registers, the 
user area is defined hyPj and 
Ri, the rest of the word is 
ignored. 



-Giving a XRSTF with a 1 in bit 6 of the PC word allows the user to handle 
his own input-output. The Monitor can also transfer control to the user with 
this instruction by programming a 1 in bit 5 of the PC word, or it may jump 
to the user program with a JRST 1 , which automatically sets User. The set 
state of this flag implements the user restrictions. 

While User is set, certain instructions are not part of the user program and 
are therefore completely unrestricted, namely those executed in the interrupt 
locations (which are not relocated) and in unrelocated trap locations 41 and 
61. Illegal instructions and UUO codes 000 and 040-077 are trapped in 
unrelocated 40; codes 100-127 are trapped in unrelocated 60. BLKI and 
BLKO can be used in the even interrupt locations, and if there is no over- 
flow, the processor returns to the interrupted user program. JSR should 
ordinarily be used in the remaining even interrupt locations, in odd interrupt 
locations following block 10 instructions, and in 41 and 61. The JSR clears 
User and should jump to the Monitor. JSP, PUSHJ, JSA and JRST are 
acceptable in that they clear User, but the first two require an accumulator 



102 



2-84 



CENTRAL PROCESSOR 



§2.16 



(all accumulators should be available to the user) and the 
latter two do not save the flags. 

After taking appropriate action, the Monitor can return to 
the user program with a JRSTF or JEN that restores the flags 
including User and User In-out. 



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2.16 OPERATION 

Most of the controls and indicators used for normal operation 
of the processor and for program debugging are located on 
the console operator panel shown here. The indicators are 
on the vertical part of the panel; in front of them are two 
rows of two-position keys and switches (keys are momentary 
contact, switches are alternate action). A key or switch is 
on or represents a 1 when the front part is down. 

The thirty-six switches in the front row and the eighteen 
at the right in the back row are respectively the data and 
address switches through which the operator can supply 
words and addresses for the program and for use in conjunc- 
tion with the operating keys and switches. The correspond- 
ence of switches to bit positions is indicated by the numbers 
at the bottom row of lights. At the left end of the back row 
are ten operating switches, which supply continuous control 
levels to the processor. At their right are ten operating keys, 
which initiate or terminate operations in the processor. The 
names of the operating keys and switches appear on the ver- 
tical part of the panel below the lights. 

Also of interest to the operator is the small panel shown 
opposite, which is located above the main panel at the left 
of the tape reader. The upper section of this panel contains 
a total hours meter and the margin-check controls. The lower 
section contains the power switch, speed controls for slowing 
down the program, switches to select the device for readin 
mode (lower part in represents a 1), and four additional 
operating switches. The normal position for these last four 
is with the upper part in; in this position FM ENB (fast 
memory enable) is on, the others are all off. 

Indicators 

When any indicator is lit the associated flipflop is 1 or the 
associated function is true. Some indicators display useful 
information while the processor is running, but many change 
too frequently and can be discussed only in terms of the 
information they display when the processor is stopped. The 
program can stop the processor only at the completion of the 
HALT instruction; the operator can stop it at the end of 



103 



§.2.16 



OPERATION 



2-85 



every instruction or memory reference, or for main- 
tenance purposes, after every step in any operation 
that uses the shift counter (shifting, multiplication, 
division, byte manipulation). 

Of the long rows of lights at the right on the 
operator panel, the top row displays the contents of 
PC, the middle row displays the instruction being 
executed or just completed, and the bottom row are 
the memory indicators. The right half of the middle 
row displays MA, the left half displays IR [see page 
1-2] . In an 10 instruction the left three instruction 
Ughts are on, the remaining instruction lights and the 
left AC light are tlje device code, and the remaining 
AC lights complete the instruction code. The I, index 
and MA lights change with each indirect reference in 
an effective address calculation; at the end of an 
instruction I is always off. 

Above the memory indicators appear two pairs of 
words, PROGRAM DATA and MEMORY DATA. If 
the triangular light beside the former pair is on, the 
indicators display a word supplied by a DATAO PI,; 
if any other data is displayed the light beside MEM- 
ORY DATA is on instead. While the processor is 
running the physical addresses used for memory refer- 
ence (the relocated address whenever relocation is in 
effect) are compared with the contents of the address 
switches. Whenever the two are equal the contents 
of the addressed location are displayed in the memory 

indicators. However, once the program loads the indicators, they can be 
changed only by the program until the operator turns on the MI program 
disable switch, executes a key function that references memory, or presses 
the reset key (see below). 

The four sets of seven lights at the left display the state of the priority 
interrupt channels [see pages 2-74 and 2-75] . The PI ACTIVE lights indicate 
which channels are on. The lOB PI REQUEST lights indicate which channels 
are receiving request signals over the in-out bus; the PI REQUEST lights 
indicate channels on which the processor has accepted requests. Except in 
the case of a program-initiated interrupt, a REQUEST light can go on only 
if the corresponding ACTIVE light is on. The PI IN PROGRESS lights indi- 
cate channels on which interrupts are currently being held; the channel that 
is actually being serviced is the lowest-numbered one whose light is on. When 
a PROGRESS light goes on, the corresponding REQUEST goes off and can- 
not go on again until PROGRESS goes off when the interrupt is dismissed. 

At the left end of the panel are a power light and these control indicators. 







M^MMwl9i§iiBM:'^^^^^ 




Above: Margin Check and 
Maintenance Panel 
Opposite: Console Operator 
Panel 



Note: If a REQUEST light 
stays on indefinitely with the 
associated PROGRESS light 
off and PC is static, check the 
PI CYC Ught on the indicator 
panel at the top of bay 2. If 
it is. on, a faulty program has 
hung up the processor. Press 
STOP. 



RUN 

The processor is in normal operation with one instruction following another. 
When the light goes off, the processor stops. 



2-86 



104 

CENTRAL PROCESSOR 



§2.16 



PI ON 

The priority interrupt system is active so interrupts can be started (this 
corresponds to CONI PI, bit 28). 



USER MODE 

The processor is in user mode (this corresponds to bit 5 of a PC word). 



If RUN and PROGRAM 
STOP are both on, the proc- 
essor is probably in an in- 
direct address loop. Press 
STOP. 



PROGRAM STOP 

IR now contains a HALT instruction. If RUN is off, MA displays an 
address one greater than that of the location containing the instruction that 
caused the halt, and PC displays the jump address (the location from which 
the next instruction will be taken if the operator presses the continue key). 



MEMORY STOP 

The processor has stopped at a memory reference. This can be due to single 
cycle operation, satisfaction of an address condition selected at ihe console, 
reference to a nonexistent memory location, or detection of a parity error. 



The remaining processor lights are on the indicator panels at the tops of 
the bays [illustrated on page C8] . Bay 2 displays AR, BR and MQ, the 
output of the AR adder, and the parity buffer which receives every word 
transmitted over the memory bus. The RL and PR lights at the lower right 
display the relocation and protection registers for the low part of the area 
assigned to a user program and the left eight bits of the relocated address 
for that part. The remaining lights are for maintenance. 

The upper four rows on4he bay 1 panel include the indicators for reader, 
punch and teletype, which are described in Chapter 3. The bottom row 
displays the information on the data hnes in the 10 bus. The AR lights at 
the upper right are the flags - FXU is Floating (exponent) Underflow, DCK 
is No Divide (divide check). OV COND is the condition that the and 1 
carries are different, ie the condition that indicates overflow. The Byte 
Interrupt flag is BYF6 in the MISC lights in the top row; User In-out is 
lOT USER in the EX lights at the center of the panel. The CPA lights in 
the top row and "the five lights under them at the left are the processor 
conditions - PDL OV is Pushdown (list) Overflow. The AS= lights in the 
middle row indicate when the (relocated) core memory address or the fast 
memory address is the same as the address switches. The remaining lights 
are for maintenance. 

The panels on the two types of memories are shown on page C9. These 
are almost exclusively for maintenance, and (as with most of the lights on 
the processor bays) if the operator must use them he should consult the 
maintenance manual and the flow charts. The ACTIVE lights indicate which 
processor currently has access to the memory. 



105 



§2.16 



OPERATION 



2-87 



Operating Keys 

Each key except STOP turns on one of the key indicators at the upper right 
on the bay 2 panel. These are for flipflops that allow the key functions to be 
repeated automatically and also allow certain of them to.be synchronized to 
the processor time chain so they can be performed while the processor is 
running. 



READ IN 

Clear all lO devices and all processor flags including User; turn on the RIM 
light in the upper right on bay 1 and the KEY RDI light in the upper right 
on bay 2. Execute DATAI £>,0 where D is the device code specified by the 
readin device switches on the small panel at the left of the reader. Then 
execute a series of BLKI D,0 instructions until the left half of location 
reaches zero, at which time turn off RIM and KEY RDI. Stop only if the 
single instruction switch is on; otherwise turn on RUN and execute the last 
word read as an instruction. [For information on the data format refer to 
page 2-72.] 

START 

Load the contents of the address switches into PC, turn on RUN, and begin 
normal operation by executing the instruction at the location specified by 
PC. 

This key function does not disturb the flags or the 10 equipment; hence 
if USER MODE is lit a user program can be started. 



If RUN is on, pressing this 
key has no effect. 

The rightmost device switch 
is for bit 9 of the instruction 
and thus selects the least sig- 
nificant octal digit (which is 
always or 4) in the device 
code. 

Caution 
Do not initiate any other key 
function while RIM is on. If 
read in must be stopped {eg 
because of a crumpled tape), 
press RESET (see below). 

If RUN is on, pressing this 
key has no effect. 



CONT (Continue) 

Turn on RUN (if it is off) and begin normal operation in the state indicated 

by the lights. 



STOP 

Turn off RUN so the processor stops before beginning the next instruction. 
Thus the processor usually stops at the end of the current instruction, which 
is displayed in the lights. However, if a key function that can be performed 
while RUN is on has been synchronized, the processor performs that func- 
tion before stopping. In either case PC points to the next instruction. 

If the processor does not reach the end of the instruction within 100 /zs, 
inhibit further effective address calculation — it is assumed the processor is 
caught in an indirect addressing loop. Pressing CONT when the processor is 
stopped in an address loop causes it to start the same instruction over. 



RESET 

Clear all 10 devices and clear the processor including all flags. Turn on the 
triangular light beside MEMORY DATA (turn off the light beside PRO- 
GRAM DATA). If RUN is on duplicate the action of the STOP key before 
clearing. 



If STOP will not stop the 
processor, pressing this key 
will. 



" 106 



2-88 



CENTRAL PROCESSOR 



§2.16 



Note that an instruction exe- 
cuted from the console can 
alter the processor state just 
like any instruction in the 
program: it can change PC by 
jumping or skipping, alter the 
flags, or even cause a non- 
existent-memory stop. 



XCT 

Execute the contents of the data switches as an instruction without incre- 
menting PC. If RUN is on, insert this instruction between two instructions 
in the program. Inhibit priority interrupts during its execution to guarantee 
that it will be finished. 

If USER MODE is ht all user restrictions apply to an instruction executed 
from the console. 



Note 

The remaining key functions all reference memory. 
They use an absolute address and all of memory is 
available to them; in other words protection and 
relocation are not in effect even if USER MODE is 
Ht. However they can set such flags as Address 
Break and Nonexistent Memory. 



EXAMINE THIS 

Display the contents of the address switches in the MA lights and the con- 
tents of the location specified by the address switches in the memory indica- 
tors. Turn on the triangular light beside MEMORY DATA (turn off the 
light beside PROGRAM DATA). If RUN is on, insert this function between 
two instructions in the program. 



If RUN is on, pressing this 
key has no effect. 



EXAMINE NEXT 

Add 1 to the address displayed in the MA lights and display the contents of 
the location specified by the incremented address in the memory indicators. 
Turn on the triangular light beside MEMORY DATA (turn off the light 
beside PROGRAM DATA). 



DEPOSIT 

Deposit the contents of the data switches in the location specified by the 
address switches. Display the address in the MA lights and the word 
deposited in the memory indicators. Turn on the triangular light beside 
MEMORY DATA (turn off the light beside PROGRAM DATA). If RUN is 
on, insert this function between two instructions in the program. 



If RUN is on, pressing this 
key has no effect. 



DEPOSIT NEXT 

Add 1 to the address displayed in the MA lights and deposit the contents of 
the data switches in the location specified by the incremented address. Dis- 
play the word deposited in the memory indicators. Turn on the triangular 
light beside MEMORY DATA (turn t»ff the light beside PROGRAM DATA). 



107 

§2.16 operation 

Caution 

Never press two keys simultaneously as the proc- 
essor may attempt to perform both functions at 
once. 



2-89 



Operating Switches 

Whenever the processor references memory at the location specified by the 
address switches (relocated if USER MODE is on), the contents of that loca- 
tion are ^displayed in the memory indicators (unless the light beside 
PROGRAM DATA is on). The group of five switches at the left of the keys 
allows the operator to make the processor halt or request an interrupt when 
reference is made to the specified location in core memory for a particular 
purpose (no action is produced by fast memory reference). The purpose is 
selected by the three address condition switches. INST FETCH selects the 
condition that access is for retrieval of an instruction (including an instruc- 
tion executed by an XCT or contained in an interrupt location or a trap for 
an unimplemented operation) or an address word in an effective address cal- 
culation. DATA FETCH selects access for retrieval of an operand (other 
than in an XCT). WRITE selects access for writing in memory. Whenever 
reference to the specified location satisfies any selected address condition, 
the processor performs the action selected by the other two switches. ADR 
STOP halts the processor with MEMORY STOP on (PC points to the instruc- 
tion that was being executed, or if the MC WR light on bay 2 is on, PC may 
point to the one following it); ADR BREAK turns on the CPA ADR BRK 
light (Address Break flag, CONI APR, bit 21) on bay 1, requesting an inter- 
rupt on the processor channel. 

The description of each switch relates the action it produces while it is on. 



AC and index register refer- 
ences can be included by 
turning off the FM ENB 
switch (see below). 



SING INST 

Whenever the processor is placed in operation, clear RUN so that it stops at 
the end of the first instruction. Hence the operator can step through a pro- 
gram one instruction at a time, by pressing START for the first one and 
CONT for subsequent ones. Each time the processor stops, the lights display 
the same information as when STOP is pressed . 

CLK FLAG (Clock flag) on bay 1 is held off to prevent clock interrupts 
while SING INST is on. Otherwise interrupts would occur at a faster rate 
than the instructions. 

SING INST will not stop the processor if a hangup prevents it from getting 
to the end of an instruction. Use STOP or RESET, 



SING CYCLE 

Whenever the processor is placed in operation, stop it with MEMORY STOP 
on at the end of the first core memory reference. Hence the operator can 
step through a program one memory reference at a time, by pressing START 
for the first one and CONT for subsequent ones. To determine what infor- 
mation is displayed in the lights, consult the flow charts. 



To stop at AC and index 
register references, turn off 
the FM ENB switch (see 
below). 



2-90 



If IGN is on (it displays a sig- 
nal from the memory), |?arity 
errors are not detected and no 
stop can occur. 



108 

CENTRAL PROCESSOR 



§2.16 



PAR STOP 

stop with MEMORY STOP on at the end of any memory reference in which 
even parity is detected in a word read. A parity stop is indicated by the fol- 
lowing: CPA PAR ERR (Parity Error flag) on bay 1 is on; and among the 
PAR lights in the bottom row on bay 2, IGN (ignore parity) and ODD are 
off, STOP is on, and BIT displays the parity bit for the word in the parity 
buffer at the left. 



NXM STOP 

Stop with MEMORY STOP on if a memory reference is attempted but the 
memory does not respond within 100 fxs. This type of stop is indicated by 
CPA NXM FLAG (Nonexistent Memory flag) on bay 1 being on. 



The key function is repeated 
once after REFT is turned 
off, but this is noticeable only 
with very long repeat delays. 



The end of a key function is 
equivalent to completion of 
all processor operations asso- 
ciated with the function only 
for read in, examine, examine 
next, deposit, and deposit 
next. In other cases the proc- 
essor continues in operation. 
Eg the execute function is 
finished once the instruction 
to be executed is set up 
internally, but the processor 
then executes that instruc- 
tion. Hence when using speed 
range 6, the operator must be 
careful not to allow the key 
function to restart before the 
processor is really finished. 



REPT 

If any key (except STOP) is pressed, then every time the key function is 
finished, wait a period of time determined by the setting of the speed control 
and repeat the given key function. If CONT is pressed and no switch is on 
that would stop the program (eg SING INST, SING CYCLE), then continue 
following the repeat delay whenever a HALT instruction is executed. Con- 
tinue to repeat the key function until RESET is pressed or REPT is turned 
off. 

The speed control includes a six-position switch that selects the delay 
range and a potentiometer for fine adjustment within the range. Delay 
ranges are as follows. 



Position 


Range 


1 


270 ms to 5.4 seconds 


2 


38 ms to 780 ms 


3 . 


3.9 ms to 78 ms 


4 


390 MS to 7.8 ms 


5 


27 MS to 540 MS 


6 


2.2 MS to 44 ms 



MI PROG DIS 

Turn on the triangular light beside MEMORY DATA (turn off the light 
beside PROGRAM DATA) and inhibit the program from displaying any in- 
formation in the memory indicators. The indicators will thus continually 
display the contents of locations selected from the console. 



REPT BYP 

If REPT is on, trigger the repeat delay at the beginning of the key function. 

Hence the function is repeated even if it does not run to coriipletion. 



109 



§2.16 OPERATION 2-91 

FM ENB 

This switch is left on for normal operation with a fast memory. Turning it 
off (lower part in) substitutes the first sixteen core locations for the fast 
memory. The switch is left off if there is no fast memory, and it can be used 
to allow stopping or breaking at fast memory references. 



SHIFT CNTR MAINT 

Stop before each step in any shift operation. Pressing CONT resumes the 
operation. Once a shift has been stopped, the processor will continue to 
stop at each step throughout the rest of the given shift operation even if the 
switch is turned off. 



At the right end of panel IJ behind the bay doors are two toggle switches. 
FP TRP causes the floating point and byte manipulation instructions (codes 
130-177) to trap to locations 60-61. MA TRP OFFSET moves the trap 
and interrupt locations to 140-161 for a second processor connected to the 
same memory. 

Inside each memory bay are switches for selecting the memory number 
and interleaving memories. Also in the memory are a power switch, a restart 
pushbutton, and a switch for single step operation (these three are located 
on the indicator panel for the MB 10 memory). 



110 



Ill 



Basic In-out Equipment 



The PDF- 10 contains three in-out devices as standard equipment: tape 
reader, tape punch, and teletype. These devices are used principally for 
communication between computer and operator using a paper medium, tape 
or form paper. 

The punch supplies output in the form of 8-channel perforated paper tape 
in either of two modes. In alphanumeric mode, 8-bit characters are proc- 
essed; in binary mode, 6-bit characters. The information punched in the 
tape can be brought into memory by the tape reader, which handles charac- 
ters in the same two modes. 

The program can type out characters on the teletype and can read charac- 
ters that have been typed in at the keyboard. This device has the slowest 
transfer rate of any, but it provides a convenient means of man-machine 
interaction. 



3.1 PAPER TAPE READER 

The reader processes 8-channei perforated paper tape photoelectrically at a 
speed of 300 lines per second. The device can operate in alphanumeric or 
binary mode, as specified by the or 1 state respectively of the Binary flag. 
In alphanumeric a single tape-moving command reads all eight channels from 
the first line encountered. In binary the device reads six channels from the 
first six lines in which hole 8 is punched and assembles the information into 
a 36-bit word. The interface contains a 36-bit buffer from which all data is 
retrieved by the processor. The reader device code is 1 04, mnemonic PTR. 



CONO PTR, 



Conditions Out, Paper Tape Reader 



71060 


/ 


X 


; 



12 13 14 



17 18 



35 



Set up the reader control register according to bits 30-35 of the effective 
conditions E as shown (a 1 in a flag bit sets the flag, a clears it). 









BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 

1 1 


27 


28 


29 


30 


31 


32 


33 34 '* 35 



3-1 



3-2 



112 

BASIC IN-OUT EQUIPMENT 

CONI PTR, Conditions In, Paper Tape Reader 



§3.1 



71064 



12 13 14 17 18 35 

Read the status of the reader into bits 27 and 30-35 of location E as shown. 



TAPE 



27 



28 



29 



BINARY BUSY 



DONE 



30 



32 



PRIORITY INTERRUPT 
ASSIGNMENT 



33 



3S 



Placing the tape in motion sets the Tape flag and it remains set as long as the 
tape is in the read head. A in bit 27 indicates that the last time an attempt 
was made to read, the reader was out of tape. 



DATAI PTR, 



Data In, Paper Tape Reader 



71044 



12 13 14 



35 



Transfer the contents of the reader buffer into location E. Clear Done and 
set Busy. 



TAPE CHANNELS 



FEED 
HOLE 



TAPE MOTION 



Setting Busy clears the reader buffer, sets the Tape flag (if it is not already 
set) and places the reader in operation. If Binary is clear, all eight channels 
from the first line on tape are read into bits 28-35 of the buffer with 
channel 1 corresponding to bit 35 (the presence of a hole produces a 1 in the 
buffer). If Binary is set, the device reads only channels 1-6, bat it reads the 
first six lines encountered in which channel 8 is punched (lines without a 
hole in channel 8 are skipped) and assembles them into a full word in the 
buffer. The first line is at the left in the word and channel 1 corresponds to 
the rightmost bit in each 6-bit byte. 

After the specified number of lines has been read, the reader clears Busy 
and sets Done, requesting an interrupt on the assigned channel. A DATAI 
brings the data into memory and also causes the reader to continue in opera- 
tion. The programmer must give a CONO to clear Busy if he does not want 
the readci to move the tape after the final DATAI is given. 

If the tape runs out or malfunctions while a read operation is in progress, 
the Tape flag is cleared and the reader shuts down. 

Timing. At 300 lines per second the reader takes 3.33 ms per alpha- 
numeric character, 20 ms per binary word if the binary characters are con- 
tiguous. After Done is set, the program has 1.6 ms to give a DATAI and 
keep the tape in continuous motion. Waiting longer causes the reader to 
shut down for 40 ms. Thus start-stop operation is Hmited to 25 lines per 
second. 



113 



§3.1 



PAPER TAPE READER 



3-3 



Examples. This program reads ten binary words (60 lines) from paper 
tape and stores them in memory beginning at location 4000. The block 
pointer is kept in accumulator PNT. 



NEXT: 



MOVE PNT,[IOWD 12,4000] ;Put pointer in PNT 



CONO 


PTR,60 


;Set up reader 


CONSO 


PTR,10 


;Watch Done 


JRST 


.-1 




BLKI 


PTR,PNT 


;Word ready, get it 


JRST 


.+2 


;Got all data 


JRST 


NEXT 


;Go gack for next word 



If instead of just waiting we wish to continue our program while the data 
is coming in, we can use the priority interrupt. The following uses channel 4 
and signals the main program that the data is ready by setting bit 35 of 
accumulator F. 



MOVE 


17, [BLKI 


PTR,[IOWD 12,4000]] 


MOVEM 


17,50 


; Set up 50 and 5 1 for channel 4 


MOVE 


17,[JSR 


DONE] 


MOVEM 


17,51 




CONO 


PTR,64 


;Set up reader on channel 4 


CONO 


PI, 12210 


;Clear PI, then activate it and turn on 
; channel 4 
;Continue program 


TRZN 


F,l 


;Check if data ready when needed 


JRST 


.-1 


;Wait if necessary 







;Interrupt routine, block done 


CONO 


PTR,0 


;Stop tape 


TRO 


F,l 


;Set F bit 35 


JEN 


©DONE 


; Dismiss and restore flags 



DONE: 



Operation. Tapes must be unoiled and opaque. The reader is located just 
above the console operator panel. To load it, place the fanfold tape stack 
vertically in the bin at the right, oriented so that the front end of the tape is 
nearer the read head and the feed holes are away from you. Lift the gate, 
take three or four folds of tape from the bin, and sHp the tape into the rea- 
der from the front. Carefully line up the feed holes with the sprocket teeth 
to avoid damaging the tape, and close the gate. Make sure that the part of 
the tape in the left bin is placed to correspond to the folds, otherwise it will 
not stack properly. If the program requires that the Tape flag be set and it is 
not, briefly press the white feed button located on the face of the reader. 
After the program has finished reading the tape, run out the remaining 
trailer by pressing the feed button. 

Indicators for the reader are on the panel at the top of bay 1 (the panel is 



114 



3-4 



BASIC IN-OUT EQUIPMENT 



§3,1 



pictured in Appendix C). Tlie paper tape reader lights in the second row 
from the bottom display the contents of the buffer. The PI assignment and 
flags are displayed in the PTR lights in the middle of the thitd row (EOT is 
the Tape flag). The remaining PTR lights are for maintenance. 



This loader is written for min- 
imum size and is quite com- 
plex. Do not approach it as a 
simple programming example. 



Readin Mode 

The only requirement (beyond those given in §2.12) for readin mode with 
paper tape is that the data must be in binary (hole 8 punched). To select 
the reader in the readin device switches, turn on the third from tlie left and 
the last on the right ( 1 04). 

The program below is the RIM 1 OB Loader, which is brought into the 
accumulators in readin mode, and then continues to read any number of 
blocks of binary data from the same tape. The tape is formatted as a series 
of blocks separated by a half-dozen lines of blank tape (tape with only feed 
holes punched). The first block is the loader in readin format. The rest of 
the tape contains any number of data blocks and ends with a transfer block. 
Each data block contains any number of words of program data, preceded 
by a standard 10 block pointer for the data only, and followed by a check- 
sum, which is the sum of all the data words and the pointer. It is recom- 
mended that the number of data words per block be limited to twenty for 
ease in repositioning the tape in case of error. The transfer block is a JRST 
to the starting location of the program, followed by a throw-away word to 
stop the reader. 



ST: 
STl 
RD: 



A: 
TBLl: 

TBL2: 



XWD 

CONO 

HRRI 

CONSO 

JRST 

DATAI 

XCT 

XCT 

SOJA 

CAME 

ADD 
SKIPL 

JRST 
AOBJN 



;14io words starting at location 1 
;Set up reader binary 
;PutRD+l in r part of A 
:Watch Done 



ADR: JRST 

CKSM=ADR+1 



-16,0 
PTR, 60 
A,RD+1 
PTR, 10 
-1 
PTR,@TBL1-RD+1(A) ;First and last words in 

;ADR, data in block 
TBL1-RD+1(A) ;TBLl-h2 first word, +1 data, 

';+0 checksum 
TBL2-RD+I(A) ;TBL2-h2 JRST, +1 data, +0 

;bad checksum 
A, ;RD+1 first word, RD data, RD-1 

;last word 
CKSM,ADR ;Compare computed checksum with 

;one read 
CKSM, 1 (ADR) ; Add word read to checksum 

CKSM,ADR ;Put first word in CKSM, skip if 

; pointer 
4, ST ;Halt if checksum bad 

ADR,RD ;If data done, go to A; otherwise wait 

; for next word 
STl ;Read in executes this. First and last 

;word of each block also put here 



§3.2 



115 

PAPER TAPE PUNCH 



The processor halts if a computed checksum does not agree with the tape. 
To reread a block, move the tape back to the preceding blank area and press 
the continue key. A halt following the transfer block is not an error - many 
programs begin by halting. 



3.2 PAPER TAPE PUNCH 

The punch perforates 8-channel tape at speeds up to 50 lines per second. !t 
can operate in alphanumeric or binary mode, as specified by the or 1 state 
respectively of the Binary flag* but in either mode a single tape-moving 
command punches only one Hne. Alphanumeric mode punches an 8-bit 
character suppHed by the program; binary mode always punches channel 8, 
never punches channel 7, and punches a 6-bit character in the remaining 
channels. The interface contains an 8-bit buffer that receives data from the 
processor. The punch device code is 100, mnemonic FTP. 



3-5 



CONO PIP, 



Conditions Out, Paper Tape Punch 



71020 


/ 


X 


Y 



12 13 14 



17 18 



3S 



Set up the punch control register according to bits 30-35 of the effective 
conditions E as shown (a 1 in a flag bit sets the flag, a clears it). 



BINARY BUSY 



DONE 



PRIORITY INTERRUPT 

ASSIGNMENT 



27 



28 



29 



30 



31 



32 



33 



34 



CONI PIP, 



Conditions In, Paper Tape Punch 



71024 


/ X 


Y 



12 13 14 17 18 

Read the status of the punch into bits 29-35 of location E as shown. 



35 







NO 
TAPE 


BINARY 


BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT 

1 1 


27 


28 


29 


30 


31 


32 


33 34 35 



A 1 in bit 29 indicates that the punch is out of tape. 



3-6 



116 

BASIC IN-OUT EQUIPMENT 

DATAO PTP, Data Out, Paper Tape Punch 



§3.2 



71014 


/ 


X 


Y 



12 13 14 



17 18 



35 



Load the contents of bits 28-35 of location £" into the punch buffer. Clear 
Done and set Busy. 



A CONO need be given only to change Binary or the PI assignment; 
DATAO sets Busy while loading the buffer. Setting Busy places the punch in 
operation. If Binary is clear, one line is punched in tape from bits 28-35 of 
the buffer with bit 35 corresponding to channel 1 (a 1 in the buffer produces 
a hole in the tape). If Binary is set, channel 8 is punched, channel 7 is not 
punched, and the remaining channels are punched from bits 30-35 of the 
buffer with bit 35 corresponding to channel 1. After punching is complete, 
the device clears Busy and sets Done, requesting an interrupt on the assigned 
channel. 

Timing, tf Busy is set when the punch motor is off, punching is auto- 
matically delayed 1 second while the motor gets up to speed. While the 
motor is on, punching is synchronized to a punijh cycle of 20 ms. After 
Done sets, the program has 10 ms within which to give a new DATAO to 
keep punching at the maximum rate; after 10 ms punching is delayed until 
the next cycle. If Busy remains clear for 5 seconds the motor turns off. 

Example. Suppose we wish to punch out the same information we read 
from tape in the examples of the previous section. We cannot use a BLKO 
as an interrupt instruction unless we first spread the 6-bit characters over 
sixty memory locations. The example uses channel 5 and assumes that other 
channels are already in use. 

MOVE A,[JSR PUNCH] 
MOVEM A,52 ; Set up channel 5 

CONO PTP, 55 ;Request mterrupt for first word 

CONO PI, 2004 ;Turn on channel 5 

;Continue program 



PUNCH: 



BYPPNT: 

CNT: 





ILDB 

AOSL 

CONO 

DATAO 

JEN 

XWD 
tD-60 



A,BY^?PNT 
CNT 
PTP, 40 
PTP, A 

©PUNCH 

440600,4000 



;Interrupt routine 

;Put byte in A 

;Got all bytes? 

;Yes, prevent interrupt after last word 

;Punch byte 



;Generate pointer here 
; Initialize count 



Operation. The punch is located behind the reader; both are in a drawer 
that pulls out from the front of the console. FanfoJd tape is fed from a box 
at the rear of the drawer. After it is punched, the tape moves into a storage 



§3.3 TELETYPE ' 3-7 

bin from which the operator may remove it through a slot on the front. 
Pushing the feed button beside the slot clears the punch buffer and punches 
blank tape as long as it is held in. Busy being set prevents the button from 
clearing the buffer, so pressing it cannot interfere with program punching. 

To load tape, first empty the chad box behind the punch. Then tear off 
the top of a box of fanfold tape (the top has a single flap; the bottom of the 
box has a small flap in the center as well as the flap that extends the full 
length of the box). Set the box in the frame at the back and thread the tape 
through the punch mechanism. The, arrows on the tape should be under- 
neath and should point in the direction of tape motion. If they are on top, 
turn the box around. If they point in the opposite direction, the box was 
opened at the wrong end; remove the box, seal up the bottom, open the top, 
and thread the tape correctly. ' 

To facihtate loading, tear or cut the end of the tape diagonally. Thread 
the tape under the out-of-tape plate, open the front guide plate (over the 
sprocket wheel), push the tape beyond the sprocket wheel, and close the 
front guide plate. Press the feed button long enough to punch about a foot 
and a half of leader. Make sure the tape is feeding and folding properly in 
the storage bin. Pushing the button labeled POWER sets No Tape, pushing 
it again clears the flag. It can be used to hold the program at bay while a 
tape is being loaded. 

To remove a length of perforated tape from the bin, first press the feed 
button long enough to provide an adequate trailer at the end of the tape 
(and also leader at the beginning of the next length of tape). Remove the 
tape from the bin and tear it off at a fold within the area in which only feed 
holes are punched. Make sure that the tape left in the bin is stacked to 
correspond to the folds; otherwise, it will not stack properly as it is being 
punched. After removal, turn the tape stack over so the beginning of the 
tape is on top, and label it with name, date, and other appropriate 
information. 

Indicators for the punch are the PTP lights in the top row of the panel 
at the top of bay 1 . The numbered lights display the last line punched. 



3.3 TELETYPE 

Two teletypewriter models are regularly available with the PDP-10 for use 
at the console: the KSR 35, which is capable of speeds up to ten characters 
per second, and the KSR 37, which can handle up to fifteen characters per 
second. The program can type out characters and can read in the characters 
produced when keys are struck at the keyboard. 

The teletype separates its input and output functions and in effect acts 
hke two devices with a single device code: each has its own Busy and Done 
flags, but the two share a common interrupt channel. Placing the code for a 
character in the output buffer causes the teletype to print the character or 
perform the designated control function. Striking a key places the code for 
the associated character in the input buffer where it can be retrieved by the 
program, but it does nothing at the teletype unless the program sends the 
code back as output. 



118 



3-8 



BASIC IN-OUT EQUIPMENT 



§3.3 



Character codes received from the teletype have eight bits wherein the 
most significant is an even parity bit. The Model 35 ignores the parity bit 
in characters transmitted to it. The Model 37 ignores the parity bit in a 
code for a printable character, but it performs no function when it receives 
a control code with incorrect parity. 

The Model 37 has the entire character set listed in the table in Appendix 
B. Lower case characters are not available on the Model 35, but transmitting 
a lower case code to the teletype causes it to print the corresponding upper 
case character. To go to the beginning of a new line the program must send 
both a carriage return, which moves the type box to the left margin, and 
a line feed, which spaces the paper. The teletype device code is 120, 
mnemonic TTY. 



CONO TTY, 



Conditions Out, Teletype 



71220 


/ 


X 


Y 



12 13 14 



1718 



35 



Set up the teletype control register according to bits 24-35 of the effective 
conditions E as shown (a 1 in bit 24 sets Test, a clears it; all other flag 
functions are produced by Is, Os have no effect). 



TEST 


CLEAR 
INPUT 
BUSY 


CLEAR 
INPUT 

DONE 


CLEAR 

OUTPUT 

BUSY 


CLEAR 

OUTPUT 

DONE 


SET 
INPUT 
BUSY 


SET 
INPUT 
DONE 


SET 

OUTPUT 

BUSY 


SET 

OUTPUT 

DONE 


PRIORITY INTERRUPT 
• ASSIGNMENT 
1 1 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 34 35 



Setting Test connects the output buffer directly to the input buffer, allowing 
the program to check out the interface logic without the line and the device. 



CONI TTY, 



Conditions In, Teletype 



71224 


/ 


X 


y 



12 13 14 17 



35 



Read the status of the teletype into bits 24 and 29-35 of location E as 
shown. 



TEST 










INPUT 
BUSY 


INPUT 
DONE 


OUTPUT 
BUSY 


OUTPUT 
DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 34 35 



DATAO TTY, Data Out, Teletype 



71214 


7 


X 


y 



12 13 14 



17 18 



35 



Load the contents of bits 28-35 of location E into the output buffer. Clear 
Output Done, set Output Busy, and enable the transmitter. 



§3.3 

DATAI TTY, Data In, Teletype 



12 13 14 



17 18 



119 

TELETYPE 



71204 


/ 


X 


Y 



35 



Transfer the contents of the input buffer into bits 28-35 of location E. 
Clear Input Done. 



3-9 



Output. A CONO need be given only to change the PI assignment; 
DATAO sets Output Busy and enables the transmitter while loading the 
buffer. Enabling the transmitter causes it to send the contents of the output 
buffer serially to the teletype. Completion of transmission clears Output 
Busy and sets Output Done, requesting an interrupt on the assigned channel. 

Input. Teletype reception requires no initiating action by the program 
except to supply a PI assignment. Striking a key transmits the code for the 
character serially to the input buffer. The beginning of reception sets Input 
Busy; completion clears Input Busy and sets Input Done, requesting an 
interrupt on the assigned channel. A DATAI brings the character into 
memory and clears Input Done. 

Timing. The Model 35 can type up to ten characters per second. After 
Output Done is set, the program has 9.09 ms to give a DATAO to keep 
typing at the maximum rate. After Input Done is set, the character is 
available for retrieval by a DATAI for 22.73 ms before another key strike 
can destroy it. 

The 37 can handle fifteen characters per second, 66.7 ms per character. 
After Output Done is set, the program has 6.67 ms to send a new character 
to maintain the maximum typing rate. After Input Done is set, the character 
is available for at least 10 ms. 

The sequence carriage return-line feed, when given in that order, allows 
sufficient time for the type box to get to the beginning of a new line. After 
tabbing, the program must wait for completion of the mechanical function 
by sending one or two rubouts. If the time is critical, the programmer 
should measure the time required for his tabs. Tabs are normally set every 
eight spaces (columns 9, 17, . . .) and require one rubout. 

Operation. The illustrations on the following two pages show the two 
teletype models. The teletype is actually two independent devices, keyboard 
and printer, which can be operated simultaneously. Power must be turned 
on by the operator. On the 35 the switch is beside the keyboard, and has an 
unmarked third position (opposite ON) which turns on power but with the 
machine off line so it can be used like a typewriter. A similar switch is 
located beneath the stand on the 37. 

The keyboard resembles that of a standard typewriter. Codes for printable 
characters on the upper parts of the key tops on the 35 are transmitted by 
using the shift key; most control codes require use of the control key. Those 
familiar with the 35 who are using the 37 for the first time should take a 
close look at the keyboard. On the 37 the shift is used for real upper case 
characters. The control key is used for some control characters, but many 



120 



3-10 



BASIC IN-OUT EQUIPMENT 



§3.3 




Teletype KSR 35 



have separate keys. Note also that both the keyboard arrangement and the 
labels differ somewhat. On both, the line feed (labeled "new line" on the 37) 
spaces the paper vertically at six lines to the inch, and must be combined 
with a return to start a new line. The local advance (feed) and return keys 
affect the printer directly and do not transmit codes. Appendix B Hsts the 
complete teletype code, ASCII characters, key combinations, and differences 
between the two models. 

Indicators for the teletype are the TTY lights in the second row of the 




^ 



panel at the top of bay 1 . The numbered lights display the last character 
typed in from the keyboard (bit 8 is parity). The ACT lights indicate 
activity in the transmitter and receiver. The remaining lights display the PI 
assignment and flags (the Input and Output Done flags are labeled TTI 
FLAG and TTO FLAG). 

Teletype manuals supplied with the equipment give complete, illustrated 
descriptions of the procedures for loading paper, changing the ribbon, and 
setting horizontal and vertical tabs. The first two procedures are fairly 



Teletype KSR 37 



122 

3-12 BASIC IN-OUT EQUIPMENT §3.3 

obvious: observe the paper or ribbon path and duplicate it. The other tasks 
are usually left for maintenance personnel. In any event, the best and easiest 
way to learn to do any of these things is to have someone who knows show 
you how. 



123 



Hardcopy Equipment 



This chapter discusses the line printer, XY plotter, card reader, and card 
punch. Like the basic in-out equipment, these devices are primarily for 
communication between computer and operator using a paper medium: form 
paper, graph paper or cards. 

The line printer provides text output at a relatively high rate. The pro- 
gram must effectively typeset each line; upon command the printer then 
prints the entire line. With the plotter, the program can produce ink draw- 
ings by controlling the incremental motion of pen on paper in a cartesian 
coordinate system. Curves and figures of any shape can be generated by 
proper combinations of motion in x and y. 

The card equipment processes standard 12-row 80-column cards. Many 
programmers find cards a convenient medium for source program input and 
for supplying data that varies from one program run to another. Cards are 
convenient to prepare manually, input is much faster than paper tape, and 
simple changes are easy to make: individual cards can be repunched, and 
cards can be added or removed from the deck. The card reader cannot be 
used in readin mode, but a standard card-reading program in readin format 
can be kept on paper tape or DECtape. A possible consideration in using 
cards is that many installations do not include an online card punch. 

These four devices are all run by the BAIO Hardcopy Control. Interface 
logic for a plotter can also be mounted in the TDIOA DECtape Control. 



4.1 LINE PRINTER 

The line printer outputs hardcopy composed of lines 132 characters long at 
a nominal rate of 300,600 or 1000 lines per minute. The standard printer 
has sixty-four printing characters available to the program. The characters 
and codes are the figure and upper case sets, codes 040-137, in the teletype 
code [Appendix B] . When a lower case code (140-176) is given, the corres- 
ponding upper case code is loaded into the buffer. Besides accepting printing 
characters, the printer responds to ten control characters, HT, CR, LP, VT, 
FF, DLE and DCl -4. All other codes are ignored. 

The printer has a 132-eharacter buffer that holds the image of a single line; 
the program must first load the buffer up to five characters at a time, and 
then give a control character to print the entire line. The buffer is loaded 
from left to right, and only the portion filled produces a printout. Hence 

4-1 



124 



4-2 



HARDCOPY EQUIPMENT 



§4.1 



Virtually any character set 
can be had on any printer by 
special order. In any event 
characters after the first 
ninety-five are always special 
order. 



Spacing other than the stan- 
dard can be produced by 
using a different format tape. 
The length of the loop should 
correspond to one or more 
pages of the printer form 
used, with holes punched at 
the lines where paper spacing 
is to stop. 



Programmers generally treat 
the data for the line printer 
and teletype identically, using 
the combination CR plus LF 
for printing and spacing. This 
way a given character string 
can be outputted on either 
device. CR is used alone only 
when the next print command 
will overprint, ie will print 
another character in a column 
position already printed. With 
this technique the program 
can produce a character such 
as "#" by overprinting a 
slash on an equal sign (or vice 
versa). 



for each line the program need send out characters (including spaces) only as 
far as the rightmost nonspace character. The characters are printed in the 
order that they pass the print hammers, and a given character is printed 
simultaneously in all positions that require it. In other words the drum has a 
row of 132 Afs, a row of A^s, etc; allAfs are printed together, all A^s together, 
and so forth. The first character printed depends only upon the position of 
the drum when the print command is given. 

Printers having more than sixty-four characters are also available. The 96- 
character printer outputs 600 lines per minute and has the entire figure, 
upper case and lower case sets, codes 040- 1 76. This is actually only ninety- 
five characters, but an option allows use of the delete code to select an extra 
character on the drum. A single delete code is ignored, but two consecutive 
177s cause the code 177 to be loaded into the' buffer. When the code for a 
printing character is the same as one for a nonprinting character and is loaded 
by giving it immediately after a delete code, the printing character is said to 
be ''hidden" under the nonprinting one. 

The 128-character printer outputs 500 lines per minute and uses the entire 
set of 7-bit codes for printing characters, with characters hidden under the 
ten control characters and also under null and delete. 

Output Format. Paper motion is controlled by a format tape loop in the 
printer. The tape has eight columns and the loop corresponds to an integral 
number of pages of the fanfold form paper. With the exception of CR, every 
control character that prints a line from the contents of the buffer produces 
a different spacing by selecting a particular tape column. The paper then 
advances until a hole is encountered in the selected column. 

The standard paper has 11 -inch pages of sixty-six lines, and the standard 
tape for these generates the formats listed below. The fourth column gives 
the hole positions in terms of the numbered lines on the tape. The tape is 
usually installed at random and then positioned by pressing the top-of-form 
button on the printer. Then the paper is adjusted so that the desired line on 
the paper corresponds to line on the tape. Ordinarily the paper is set with 
the print hammers at the fourth Hne, so all but one of these formats leaves 
a three-line margin at the top and a margin of at least three lines at the 
bottom of each page. 



Character 


Column 


Normal meaning 


Hole positions 


FF(014) 


1 


Top of form 


LineO 


CR(015) 


None 


No spacing (paper 
motion inhibited) 




LF(012) 


8 


Single space with auto- 


Every line from 






matic top of form after 


to 59 




' 


every 60 impressions 




DCl (021) 


3 


Double space with auto- 


Every even num- 






matic top of form after 


bered Hne from 






every 30 impressions 


to 58 


DC2 (022) 


4 


Triple space with auto- 


Every third line 






matic top of form after 


from to 57 






every 20 impressions 





125 

§4.1 LINE PRINTER 4-3 

DC3 (023) 5 Single space Every line 

DC4(024) 6 Space one sixth of a Lines 0, 10, 20 

page 30, 40, 50 

VT(013) 7 Space one third of a Lines 0, 20, 40 

page 
DLE (020) 2 Space half a page Lines 0, 30 

The actual printer action of advancing the paper to the next hole in the tape 
produces the "normal" format only if the program consistently selects the 
same tape column. Always using DCl to print produces double spaced text 
from line 4 to line 62 on every page. But if the last print command spaced to 
an odd numbered line, DCl moves the paper only one line. 

Printing Speed. The printer is available in five models with differing 
printing speeds. 



Printer 


Nominal printing 

speed in lines 

per minute 


Drum rotation 
in rpm 


Time per 

revolution 

in ms 


LPIOA 


300 


333 


180 


LPIOB 


600 


750 


80 


LPIOC 


1000 


1250 


48 


96 Character 


600 


750 


80 


128 Character 


500 


550 


109 



Printing begins as soon as a print command is given and terminates when 
the last required character is printed, ie without necessarily waiting for a 
complete drum revolution. Therefore print time depends on the initial drum 
position and the number of characters that must pass the print head before 
the last is printed. No time is required for spaces: the printer produces 
spaces in a line by not printing anything in the columns corresponding to the 
buffer positions that hold space characters. As a given character is printed, 
space codes replace the codes for the character in all buffer positions that 
hold it, and printing ceases when the buffer is filled with spaces. 

A complete print cycle consists of the print time plus the time required 
for advancing the paper; paper spacing begins immediately after printing ter- 
minates, and further printing is inhibited while the paper is moving. It takes 
about 12 ms to advance the paper one line, about 6-8 ms for each additional 
line. If the buffer is loaded only with spaces, the print cycle consists entirely 
of paper spacing. 

Using an ordinary distribution of characters results in printing at or 
slightly above the nominal speed. Printing is faster however if paper spacing 
occurs while unused characters are passing the print head. Eg text that uses 
only the alphabet can be printed at the full drum rotation speed. 

Instructions. The printer has the usual instructions for sending and reading 
conditions, but after initial setup it can be controlled entirely by the charac- 
ters sent by a string of DATAOs. The program supplies five characters at a 
time to a 35-bit character buffer in the printer interface. The interface proc- 
esses the characters from left to right loading valid data characters into the 



126 



4-4 



HARDCOPY EQUIPMENT 



§4.1 



line buffer, ignoring invalid characters, and sending control signals to the 
printer when a control character is encountered. The printer device code is 
124, mnemonic LPT. 



CONO LPT, 



Conditions Out, Line Printer 



7 12 6 


/ 


X 


Y 



12 13 14 



17 18 



35 



Perform the function given below if specified by a 1 in bit 25 and set up the 
printer control register according to bits 30-35 of the effective conditions £ 
as shown (a 1 in a flag bit sets the flag, a clears it). 





CLEAR 
PRINTER 






BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT - ERROR 

1 1 


PRIORITY INTERRUPT 

ASSIGNMENT - DONE 

1 1 


24 


25 


26 


27 


28 


29 


30 31 32 


33 34 35 



Power turnon and the 10 
reset signal generated by 
CONO APR, 200000 dupli- 
cate this clear function. 



If bit 25 is 1, clear Done, set Busy, clear the interface logic, and trigger a 
print cycle to clear the line buffer. The cycle clears the buffer by replacing 
the characters in it with spaces, and the time required is the same as would 
be required to print whatever is in it. Completion of the cycle clears Busy 
and sets Done, requesting an interrupt on the channel assigned by bits 
33-35. 



24 



25 



CON I LPT, 



Conditions In, Line Printer 



71264 


/ 


X 


Y 



12 13 14 17 18 

Read the status of the printer into bits 24-35 of location E as shown. 



35 



128 


96 




ERROR 


BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT - ERROR 

1 1 


PRIORITY INTERRUPT 
ASSIGNMENT - DONE 



26 



27 



28 



29 



30 



31 



32 



33 



34 



35 



A 1 in bit 24 indicates that the printer has a 1 28-character drum; a 1 in bit 
25 indicates that at least 95 characters are available to the program. 



DATAO LPT, 



Data Out, Line Printer 



7 1254 


/ 


X 


Y 



12 13 14 



1718 



35 



Load the contents of bits 0-34 of location E into the character buffer, clear 
Done, set Busy, and trigger the interface processing cycle. The format of the 



127 

§4.1 LINE PRINTER 

data word and the order in which the characters are processed is as shown. 



FIRST 


SECOND 


THIRD 


FOURTH FIFTH 





67 



13 14 



20 21 



27 28 



34 



4-5 

Characters are assembled into 
words in this manner by an 
IDPB loop or an ASCII or 
ASCIZ pseudoinstruction. 



Following power turnon, the Error flag (CONI bit 27) is set if the printer 
cable is not connected or any other condition exists that makes the printer 
unavailable to the program [these other conditions are given in the discussion 
of printer operation at the end of the section]. If Error is set when a CONO 
gives an error PI assignment (with bits 30-32 of £"), there is an immediate 
interrupt request on the error channel. Barring accident or hardware mal- 
function, an error interrupt is likely to occur during a printout run only 
when the printer is about to run out of paper or the operator stops it (in 
either case Error sets and the printer stops when the buffer is empty 
following the printing of a line). 

At the beginning of a print run the program should give a CONO to clear 
the line buffer and assign the PI channels. After that a CONO need .be given 
only to change the PI assignments; each DATAO starts the character-proc- 
essing operations of the interface while loading the character buffer. The 
interface processes the characters from left to right, starting each character 
cycle when the line buffer is ready. Printing characters are simply sent to the 
buffer, with lower case codes translated to upper case for a 64-character 
printer. Unused codes are ignored. The interface responds as follows when a 
control character is encountered. ^ 

♦ A horizontal tab (HT) is simulated by sending a string of spaces to the line 
buffer. Tab stops are every eight columns (9, 17, . . .). The interface always 
sends at least one space, and then sends as many more as are necessary for 
the next character to be at a tab stop. Thus if a DATAO gives the sequence 

A HT B 

where A is placed in column 7, B will go into column 9. But if ^ goes into 
column 8, B will go into column 17. 

♦ Upon encountering any other printer control character, the interface 
signals the printer to print the contents of the line buffer, and unless the 
character is CR, it also selects a format tape column to space the paper as 
listed in the format discussion at the beginning of this section. When the 
buffer again becomes available, subsequent characters-will be loaded starting 
in column 1. If printing is caused by a CR, the next line will overprint unless 
the paper is advanced before any nonspace characters are loaded into the 
buffer. 

If the buffer is filled with 132 characters and the next character does not 
cause printing, the interface simulates a line feed to print and advance the 
paper, and then loads the next character at' column 1 for the new line. If the 
program tabs to the end of a line, the interface simulates a Hne feed and also 
tabs at the beginning of the next line. In other words a printing character 
following the tab will be loaded at column 9 for the new line. 

When the interface finishes processing the five characters supplied by a 



these tabs are the same as 
the ones ordinarily used on 
the teletype. 



128 

4-6 HARDCOPY EQUIPMENT §4.1 

DATAO, it dears Busy and sets Done, requesting an interrupt on the channel 
assigned by bits 33-35 of the conditions out. 

Timing. The time from one DATAO to the next while the program is 
loading the buffer is simply the time required by the interface to process five 
characters. Loading each printing character, including each space in a 
horizontal tab, takes 10 /xs. Skipping an illegal character takes 8 jus. 

If the fifth character causes printing, Done is set immediately and the 
program can give a DATAO to send the first set of characters for the next 
line. However, the interface does not begin processing the new characters 
until the buffer becomes available after the printer finishes printing the 
previous line. If printing is produced by any character before the last, the 
print time elapses before the interface processes the next character in the 
current set. 

The overall time required for a print run is the total printing and spacing 
time for all lines as given above in the discussion of the printing speed. The 
time required to process individual characters is a consideration in pro- 
gramming the DATAOs that load the buffer, but buffer loading time is not 
a factor in total printer operating time except when loading characters for 
overprinting (following a CR). This is because the buffer becomes available 
while the paper is moving, in plenty of time for the program to load it before 
the paper stops. 

Examples. In the first example, which uses the line printer without the 
interrupt, we have simply filled in the missing part of the print subroutine 
given at the top of page 2-61 (it prints the characters that accompany the 
calling sequence given at the bottom of page 2-60). 

PRINT: HRLI T,440700 



ILDB 


CH,T 




JUMPE 


CH,1(T) 




CONSZ 


LPT, 200 


;Skip when printer not busy 


JRST 


.-1 


;Wait for Busy to clear 


LSH 


CH,1 


;Shift character to bits 28-34 



DATAO LPT,CH ;Send character to printer 

JRST PRINT+1 

The same program could be used for output on the teletype by making the 
substitution 

CONSZ LPT, 200 ^ CONSZ TTY,20 

and deleting the LSH CH,1.. 

The above is perhaps an overly simple example. It assumes the line buffer 
is clear initially and the printer is available. Moreover the processor spends 
most of its time waiting. Characters are processed individually in order to 
detect the null, but if the processor has anything else to do, it would be 
much more efficient to use the interrupt and send five characters at a time. 

In the following example the main program sets up each print run by 
giving a JSR SETUP. The number of words prmted and the starting location 
of the block containing them are determined by the contents of PNTRl. 
Once a run is set up, the program can change the contents of PNTRl for 
the next one. 



129 



§4.1 
SETUP: 



LINE PRINTER 



4-7 



PNTRl: 
PNTR: 

ERROR: 





SKIPGE 

JRST 

MOVE 

MOVEM 

MOVE 

MOVEM 

MOVE 

MOVEM 

CONO 

CONO 

JRST 





CONO 



PNTR 
-1 
T 
T 
T 



;Wait for current 10 to finish 
[JSR ERROR] 

42 ; Channel 1 for error 

[JSR DATA] 



T,44 
T,PNTR1 
T,PNTR 
LPT, 20 12 
PI, 2340 
©SETUP 



LPT, 2 



;Channel 2 for data 

;Set up new 10 block pointer 
;Clear printer, assign channels 
:Turn on PI and channels 



DATA: 



JEN 


©ERROR 



CONO 


LPT, 12 


BLKO 


LPT,PNTR 


CONO 


LPT,0 


JEN 


@DATA 



;Drop error request by dropping error 

;PI assignment 

; Start typing error message 



; Reassign error channel 
;Send out word 
;Tuni off printer 



Operation. The 600-line-per-minute printer is illustrated on the following 
page. At the left on the front of the printer are two round indicators and 
two columns of square buttons and indicators, some of which are not used. 
The round lights indicate whether the printer has power: green light for 
power on, red for off. 

The buttons at tlje top of the columns operate the printer. Pushing 
START places the printer on line so it can respond to the program (the 
button is lit while the unit is on line). Pushing STOP takes the unit off Une; 
the operator can then use the TOP OF FORM button to position the paper 
(or the format tape). If the program has left anything in the buffer, it can 
be printed by pressing MANUAL PRINT. The maintenance button TEST 
can also be used while STOP is lit. START, STOP and TOP OF FORM are 
duplicated at the rear of the printer. 

At the bottom of the columns are four alarm lights that indicate when the 
paper supply is low, the printer is out of paper or the paper is broken, the 
yoke is open, or there is a circuit malfunction (ALARM STATUS). When 
the operator presses STOP or there is a paper low alert, START does not go 
out until the buffer is empty (in other words until the printer finishes 
printing a line currently being loaded or printed). START goes out immedi- 
ately if any other alarm condition occurs or power fails. When START is 
out or the cable to the interface is not connected, the Error flag is set and 
the printer cannot respond to the program. 



End of clear function sets 
Done, requesting a data 
interrupt. 



4-8 



130 

HARDCOPY EQUIPMENT 



§4.1 



^swmmfmBmm^^^m^^mm 




Line Printer LP 1 OB 



The lights for the interface are in the top two rows on the hardcopy 
control indicator panel [illustrated on the opposite page] . The top row dis- 
plays the contents of the character buffer; the 7-bit characters are shifted 
left for processing. The shift and column counters at the left end of the 
second row indicate the last character processed (0-4) and the last buffer 
position loaded. The group of lights at the right display the status condi- 



§4.2 



131 

I'LOIIER 



4-9 



iPi^^siSiH^siiiiiiSiiiii^ii 



■S^f|^S^g»?^i&^, 




tions. Of the group in the center, BUFF AVAIL indicates the line buffer is 
ready for the next character; the remaining lights are for maintenance. 

To load paper, press STOP. If START does not go out, the program 
probably left the last line in the buffer: press MANUAL. When printing is 
complete the light will go out. Open the printer cover. At the front are two 
toggle switches: switch both of them to OPEN. The printer yoke will slide 
forward. Lift the guide plates over the two pairs of tractors, pull out the 
remaining paper, and press TOP OF FORM to line up the spacing format 
tape. Bring the beginning of the paper up behind the yoke, over the top and 
through the rollers on the back. Move the paper until line 4 of a page is 
lined up with the print hammers (at most installations the point at which the 
fold should come is marked). Make sure the tractor wheels engage the holes 
at the edges of the paper, close the guide plates, switch the toggles to 
CLOSE, close the cover, and press START. 

All of the larger and faster printers are as described above i On the slowest 
printer the lights are at the right, the single PAPER ALARM indicates the 
paper is either low or broken, and there are no buttons on the back. With 
the cover open the yoke is controlled by two unmarked plastic switches on 
either side at the top. Pressing them in at the end nearer the front opens the 
yoke. This printer has only one pair of tractors, but it has a pair of bars 
below the yoke. The paper must go over the stationary bar and under the 
movable one. 



Indicator Panel, 
Hardcopy Control 



4.2 PLOTTER 



The XYIO plotter control interfaces the PDP-10 central processor to various 
plotters that use cartesian coordinates. The models most frequently used are 
manufactured by Calcomp, but others can be accommodated. The following 
lists the type and paper size of the most commonly supplied Calcomp 
models. 



4-10 



132 






HARDCOPY EQUIPMENT 




Calcomp model 


Type 


Paper size in inches 


502, 602 


Bed 


31 X 34 


518,618 


Bed 


54 X 72 


563,663 


Drum 


29^2 X 1440 


565,665 


Drum 


11 X 1440 



.§4.2 



These are high accuracy, incremental digital plotters that produce fine 
quality ink plots of computer-generated data. Bidirectional stepping motors 
provide individual increments of motion in either coordinate or both at once. 
The program draws a continuous sequence of line segments by controlling 
the relative motion of pen and paper with the pen lowered, and it can raise 
the pen for repositioning. 

Motion in y is movement of the pen carriage along a pair of rods. Motion 
in X is movement of the entire carriage-and-rod mechanism on a bed plotter, 
movement of the paper underneath the carriage on the drum type. On a bed 
plotter the coordinate directions are the standard ones when viewing the 
device from the front: positive x to the right, positive y to the back. The 
coordinate system on a drum is in the standard orientation when the viewer 
is standing at the right side, unrolling the paper from the drum with his left 
hand. In other words positive y is movement of the pen from right to left 
across the drum, positive x is drum rotation downward at the front (drawing 
a hne toward the paper supply roll at the back). 

The step sizes and plotting speeds available with the various Calcomp 
models are the following. " 



Calcomp plotters in the 600 
series have two step sizes and 
two plotting speeds: a switch 
at the back selects the step 
size, delay settings in the 
plotter control determine the 
speed. 



Model 


Step size 


Plotting speed in 
steps per second 


502 


All sizes 


300 




.005 inch 


200 


518 


.002 inch 
.1 mm 


450 
200 




.05 mm 


400 




.010 inch 


200 


563 


.005 inch 


300 




.1 mm 


300 


565 


All sizes 


300 


602 


All sizes 


450/900 


618 


.005/.0025 inch 
.002/.001 inch 
.1/.05 mm 
.05/.025 mm 


200/400 
450/900 
200/400 
^50/900 


663 


.010/.005inch 
.005/.0025 inch 
.0025/.00 125 inch 


350/700 
450/900 
450/900 


665 


All sizes 


450/900 



133 



^§4.2 



PLOTTER 



4-11 




The program can draw any complete figure by giving a string of DATAOs, 
each of which supplies the information for one step. The plotter device code 
is 140, mnemonic PLT. 



Calcomp Drum Plottc 
Model 565 



CO NO PLT, 



Conditions Out, Plotter 



71420 


/ 


X 


Y 



12 13 14 



Set up the plotter control register according to bits 31-35 of the effective 
conditions E as shown (a 1 in a flag bit sets the flag, a clears it). 











BUSY 


DONE 


PRIORITY INTERRUPT 

ASSIGNMENT 
1 1 


27 


28 


29 


30 


31 


32 


33 34 35 



4-12 



134 

HARDCOPY EQUIPMENT 

CONI PIT, Conditions In, Plotter 



§4.2 



72424 


/ 


X 


Y 



12 13 14 17 18 35 

Read the status of the plotter into bits 30-35 of location E as shown. 









POWER 
ON 


BUSY 


DONE 


PRIORITY INTERRUPT 
ASSIGNMENT 

1 1 


27 


28 


29 


30 


31 


32 


33 34 35 



Power On is not available on all plotters. 



DATAO PLT. 



Data Out, Plotter 



7 14 14 


/ 


X 


Y 



12 13 14 



17 18 



35 



Clear Done, set Busy, and move the pen as specified by bits 30-35 of the 
contents of location E as shown (a 1 in a bit produces the indicated motion, 
a has no effect). 



RAISE 

PEN 


LOWER 
PEN 


-AX 

(DRUM 
UP) 


+AX 

(DRUM 

DOWN) 


+Ar 

(CARRIAGE 
LEFT) 


-Ar 

(CARRIAGE 
RIGHT) 



30 



31 



32 



33 



34 



35 



A CONO need be given only to change the PI assignment; DATAO places 
the plotter in operation by supplying plotting data. After sufficient time has 
elapsed for the device to carry out the specified action, the control clears 
Busy and sets Done, requesting an interrupt on the assigned channel. 

To avoid drawing line segments shorter than one step, do not raise or 
lower the pen in the same DATAO that calls for xy motion. The conse- 
quences of specifying contradictory movements cannot be predicted. 

Timing. Lowering the pen takes 60 ms, raising it takes 10 ms. The time 
required to move one step in either or both coordinates depends on the 
plotting speed as follows. 



Plotting speed in 
steps per second 


Time per step in ms 


200 


2.5 


300 


1.66 


350 


1.45 


400 


1.25 


450 


1.10 


700 


,70 


900 


.51 



135 



§4.2 



PLOTTER 



4-13 



Example. The plotting commands sent out by this program are contained 
six to a word in WC words beginning at location BUFFER. The interrupt 
routine uses one accumulator which is shared with the main program and 
other channels. 





CONSZ 


PLT,7 


;Wait until previous run finished as 




JRST 


.-1 


; indicated by no PI assignment 




MOVE 


T,[JSR DATA] 




MOVEM 


T,50 


;Set up channel 4 




MOVEI 


T,WC*6 


;Set up count for plotting commands 




MOVEM 


T,COUNT 






MOVE 


T, [POINT 


6,BUFFER] ;Initiate byte pointer 




MOVEM 


T,CHARP 






CONO 


PLT,4 


; Assign channel 




CONO 


PI, 22 10 


;Turn on PI and channel 




DATAO 


PLT,PUP 


; Raise pen to trigger first interrupt 


DATA: 











SOSGE 


COUNT 


;Is plot finished? 




JRST 


DATAl 


;Yes 




MOVEM 


T,TSAVE 


;Save T 




ILDB 


T,CHARP 


;Get next plotting command 




DATAO 


PLT,T 


;Plot point 




MOVE 


T,TSAVE 


;Restore T 




JEN 


@DATA 




PUP: 


40 






TSAVE: 









COUNT: 









CHARP: 









DATAl: 


CONO 


PLT,0 


;Disconnect plotter from interrupt 




DATAO 


PLT,PUP 


;Raise pen 




JEN 


©DATA 





Operation. On a drum plotter the supply roll is behind the drum. Bring 
the paper over the drum, down in front, and above and behind the pickup 
roll underneath the drum (use a piece of masking tape to attach the paper, 
or roll some onto the tube). 

The controls are on the front [refer to the illustration on page 4-11]. To 
put the plotter on line simply turn on the power and the chart drive. The 
remaining controls are for manual operation: raising and lowering the pen, 
moving the carriage and drum in either direction, rapidly or single step. The 
switch that selects the step size on a 600-series plotter is on the back. The 
bed plotter has similar controls. 

Lights for the plotter are the group at the right end in the bottom ro\v on 
the hardcopy control indicator panel [page 4-9] . These display the status 
conditions and the plotting data supplied by the last DATAO. If the -plotter 
interface is mounted in a DECtape control, there are no lights. 



The asterisk is the sign for 
multiplication in Macro. 

l*dlNT is a pseudoinstruction 
that causes Macro to gener- 
ate a byte pointer from the 
three arguments that follow 
it. In order these arguments 
are the byte length in deci- 
mal, the address of the loca- 
tion containing the byte, and 
the position of the rightmost 
bit of the byte as the decimal 
number of the bit in the 
word. If the last argument is 
omitted, Macro takes it as 
-1; in other words, after 
being incremented the pointer 
will point to the first byte. 
The left half of the pointer 
generated here is 440600. 



4-14 



136 

HARDCOFY EQDH'MENT 

4.3 CARD READER 



§4.3 



The card reader handles standard 12-row 80-column cards at speeds up to 
1000 cards per minute (833 if power is 50 Hz). Once started, an entire card 
is read column by column. The reader supplies each column to the processor 
as twelve bits, and the program can translate in any way it wishes; the 
standard DEC character representations and the translation to ASCII made 
by the Monitor are given in Appendix B. Of course the data can simply be in 
binary at three columns per word (a 7 and 9 punch in the first column is the 
standard indication that the rest of the card contains binary data). 

The interface contains a 1 2-bit buffer from which each column ia retrieved 
by the processor. The reader device code is 150, mnemonic CR. 



CONO CR, 



Conditions Out Card Reader 



7 1520 



J 



12 13 14 



1718 



35 



Assign the interrupt channel specified by bits 33-35 of E and perform the 
functions specified by bits 23-32 as shown (in bits 27 and 29 a 1 enables 
the given flag to interrupt, a disables it; in all other bits a 1 produces the 
indicated function, a has no effect). 





















ENABLE 
TROUBLE 
INTERRUPTS 

/ 


ENABLE 
READY 
TO READ 
INTERRUPTS 


















CLEAR 
READER 


OFFSET 
CARD 




READ 
CARD 


/ 


CLEAR 
DATA 
MISSED 


/ 


CLEAR 
END 
OF 
FILE 


CLEAR 
END 
OF 

CARD 


CLEAR 
DATA 
READY 


PRIORITY 
INTERRUPT 
ASSIGNMENT 

1 1 


18 


19 


20 


21 


22 


23 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 34 35 



With the console model, off- 
setting a card places it in a 
separate stacker. 



Notes. 

23 



24 



Dismiss the PI assignment (assign zero); clear flags Reading Card, 
Data Missed, End of File, End of Card, Data Ready, Trouble 
Interrupt Enabled, Ready to Read Interrupt Enabled; clear the card 
column buffer; and disable any read command given by a CONO if 
the reader has not yet started the card. If any action specified by the 
rest of the CONO bits conflicts with these actions, the clear function 
has precedence. 

If a card is currently being processed in the reader (Card In Reader, 
COM bit 24, is 1), offset it when it is placed in the stacker. The card 
will actually stick out about a half inch from the rest of the stacked 
deck. 



§4.3 
CONI CR, 



137 



CARD READER 



4-15 



Conditions In, Card Reader 



71524 


/ 


X 


Y 



12 13 14 17 18 

Read the status of the reader into the right half of location E as shown. 



3S 



TROUBLE 

INTERRUPl 

ENABLED 

\ 


READY 
TO READ 
INTERRUPT 
ENABLED 














* 


* 


* 


* 


* 


* 




1 


/ 


PICK 
FAILURE 


PHOTO 
CELL 
ERROR 


CARD 
MOTION 
ERROR 


STOP 


CARD 

IN 

READER 


HOPPER 
EMPTY- 
STACKER 
FULL 


READING 
CARD 


TROUBLE 


DATA 
MISSED 


READY 
TO 
READ 


END 
OF 
FILE 


END 
OF 
CARD 


DATA 
READY 


PRIORITY 

INTERRUPT 

ASSIGNMENT 

1 1 


16 


19 


20 


21 


22 


23 


24 


25 


26 


27 


28 


29 


30 


31- 


32 


33 34 35 



Notes. 

Interrupts are requested on the assigned channel by the setting of Data 
Ready, Data Missed, End of Card, End of File, and if enabled, Trouble and 
Ready to Read. 

20 The reader has received a read command but has failed to bring in 
a card from the hopper. 

21 The reader has failed to read a card properly and maintenance is 
probably required. The program should be dubious of any data 
taken from the card being read when the error occurred. 

22 A card has failed to move properly through the reader (it has 
probably slipped). The program should be dubious of any data taken 
from the card being read when the error occurred. 

23 Reader power is on but the reader is or soon will be unavailable to 
the program either because the operator has pressed the stop button 
or there is a trouble condition (bit 27). If Stop is set while a card is 
being read, the reader usually finishes it; only a power failure can 
stop the reader in the middle of a card. 

24 The reader has brought a card in from the hopper and has not yet 
finished reading it. The program can give a CONO offset command 
while this bit is 1 . 

26 The reader has accepted a read command and has not yet finished 
reading the card. 

27 Bit 20, 21, 22 or 25 is 1. If bit 18 is also 1, the setting of Trouble 
requests an interrupt on the assigned channel. 

Any condition that sets Trouble also sets Stop (bit 23) and the 
reader will stop at the end of the current card (of course a pick 
failure prevents the reader from even starting a card). Although a 1 
in bit 27 does not necessarily imply an error or malfunction, it 
always requires operator intervention. If bit 25 is 1 it is very likely 
that the only trouble is the hopper is empty or the stacker is full. 

28 The program failed to retrieve a column of data before the next 
column was loaded into the buffer by the reader. 



* These bits cause interrupts. 



4-16 



The usual procedure is to put 
an end-of-file card at the end 
of the deck rather than use 
the button. Actually the but- 
ton can be used to signal the 
program for any purpose pro- 
vided the reader is off line 
(stopped). 



138 

HARDCOPY EQUIPMENT 



§4.3 



29 The reader is ready to accept a read command. If bit 19 is 1, the 
setting of Ready to Read requests an interrupt on the assigned 
channel. 

30 The reader has stopped (probably because the hopper is empty) and 
the operator has pressed the end-of-file button. 



DATAI CR. 



Data In, Card Reader 



71504 


/ 


X 


Y 



17 18 



35 



Clear Data Ready, and transfer the contents of the card column buffer into 
bits 24-35 of location E where the correspondence of card rows to bit 
positions is as shown. 



ROW 12 


ROW 11 


ROWO 


ROW 1 


ROW 2 


ROW 3 


ROW 4 


ROW S 


ROW 6 


ROW 7 


ROW 8 


ROW 9 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 


34 


35 



If the program does not re- 
trieve the final column and a 
CONO that starts a new card 
does not clear Data Ready, 
Data Missed will be set by the 
first column in the new card. 



If the reader operates on 50 
Hz power, all times must be 
increased by 20 per cent. 



The program must give a CONO with a 1 in bit 26 to start every card. 
This read card command waits until the reader is ready, at which time Read- 
ing Card sets and the reader card cycle begins. Movement of a card in from 
the hopper sets Card in Reader. As each column is loaded into the buffer, 
Data Ready sets, requesting an interrupt on the assigned channel. The 
program must respond with a DATAI to transfer the column to memory and 
clear Data Ready. If Data Ready is still set when the next column is loaded 
into the buffer, Data Missed is set, requesting a second interrupt. 

After all eighty columns have been read, Card in Reader goes off, clearing 
Reading Card and setting End of Card, which requests an interrupt. The 
card then moves out to the stacker, and when the device is ready to begin a 
new card cycle. Ready to Read goes on, but only if no new read card 
command has been given. If a read card command is already waiting when 
the reader becomes ready, it simply accepts the command and Ready to 
Read remains off. If no command is . waiting, Ready to Read goes on, 
requesting an interrupt if enabled (COM bit 19 is 1), and it goes off auto- 
matically when a new command is given. 

Timing. After Reading Card sets, 1 8 ms elapse before Card in Reader goes 
on. The first Data Ready occurs 1 .8 ms later. Subsequent columns are ready 
every 370 jus - the program must give a DATAI within 350 jUS after each 
setting of Data Ready. Total time from first to last Data Ready is 29.2 ms. 
After the final Data Ready, 1 .8 ms elapse before Card in Reader and Reading 
Card clear and End of Card sets. The program then has 9.2 ms within which 
to give a new CONO read card command to keep the reader going at the 
maximum rate. Ready to Read goes on at the end of this period if no new 
command appears. 

When the last card in a deck is read, the hopper empty signal is simul- 



139 



§4.3 



CARD READER 



4-17 




taneous with End of Card. 

Operation. The reader has a 
hopper and stacker capacity of 
1000 cards. To load a deck, 
first fan the cards and jog 
them on the reader shelf. Turn 
the deck over and put the first 
hundred cards (about an inch 
of the deck) into the hopper 
(upper right) with the 9 edge 
against the back so column 1 
is read first. Place the rest of 
the deck on top of the first 
part. Cards can be added to 
the hopper while the reader is 
running, but always stop the 
reader before removing cards 
from the stacker. 

The reader is operated 
by the buttons at the left. 
The alternate-action POWER 
switch lights green when 
power is on. Pushing START 
places the reader on line so the 
program can read cards. Pushing STOP turns off the reader, taking it off line. 

The lights at the right indicate an empty hopper, a full stacker, a pick 
failure, a card motion error, and a photocell output that is too weak or too 
strong. When one of these lights goes on the STOP light also goes on (the 
reader always finishes the current card before stopping). Do not attempt to 
reread a worn or damaged card that has caused a pick failure or motion 
error ~ duplicate it first. If any trouble light remains on after the problem is 
corrected press the CLEAR button; this turns off both the lights and the 
corresponding status signals read by a CONI. Press START to allow the 
program to continue reading the deck. If the trouble persists, enter it in the 
system log and notify maintenance personnel. 

Pressing the END OF FILE button (at the right) when the reader is off 
line, as when the hopper is empty, sets the End of File flag. When the TEST 
MODE light is on, the reader processes cards off line (the test switch is 
behind the panel under the shelf). 

Lights for the interface are in the bottom two rows on the hardcopy 
control indicator panel [page 4-9] . The left section of the upper row dis- 
plays the contents of the card column buffer; the lights are marked by card 
row. The left section of the bottom row displays bits 24-35 of the status 
conditions. (The second light from the left is labeled HOP EMPTY, but it 
goes on when the hopper is empty or the stacker is full.) Of the five lights 
in the center, the left one is the momentary offset signal. READ is on when 
a read command has been given but the reader is not yet ready. The next 
two lights display bits 18 and 19 of the status conditions, and the last light 
is on while an interrupt is being requested whatever the cause. 



Card Reader 



4-18 



140 

HARlH'OrY lOUIi'MCNI 



§4.4 



Also available is a console model reader that has a 2000-card hopper and 
two 2000-card stackers. In use it differs from the compact model only in 
that offsetting a card places it in the second stacker (the one on the right), 
and cards can be removed from the stackers while the reader is running. 



4.4 CARD PUNCH 

The card punch handles standard 12-row 80-column cards at speeds up to 
200 cards per minute if all eighty columns are punched, 365 cards per minute 
if only the first sixteen columns are punched. The processor must supply 
each column to the punch as twelve bits, and the program can generate this 
data by any procedure it wishes; the standard DEC character representations 
and the translation from ASCII made by the Monitor are given in Appendix 
B. Of course the data can simply b^ in binary at three columns per word 
(punching rows 7 and 9 in the first column is the standard procedure for in- 
dicating that the rest of the card contains binary data). 

A card is taken from the hopper only when the program supplies data for 
the first column. In the interface is a 1 2-bit buffer to which the processor 
sends each column, but the punch has a 48-bit buffer, and it punches four 
columns at a time from each set of four 1 2-bit bytes sent through the inter- 
face. The program can send a card to the stacker after punching any number 
of columns. The punch device code is 110, mnemonic CDP. 



CONO CDP, 



Conditions Out, Card Punch 



7 1120 



2 13 14 



17 18 



35 



Assign the interrupt channel specified by bits 33-35 of the effective condi- 
tions E and perform the functions specified by bits 20-32 as shown (a 1 in a 
bit produces the indicated function, a has no effect). 



CLEAR 
PUNCH 



OFFSET 
CARD 



EJECT 
CARD 



DISABLE I ENABLE 

TROUBLE 

INTERRUPTS 

I 



CLEAR 
ERROR 



DISABLE I ENABLE 
END OF CARD 



CLEAR 
END 
OF 

CARD 



SET 

PUNCH 

ON 



CLEAR 1 SET 

DATA 
REQUEST 



PRIORITY 

INTERRUPT 

ASSIGNMENT 

_J L- 



20 



22 



23 



24 



25 



26 



27 



28 



29 



50 



32 



33 



34 



35 



Notes. 



20 Clear flags Trouble Interrupt Enabled, Error, End of Card Enabled, 
End of Card, Punch On, Busy, Data Request; clear the card column 
buffer. If any action specified by the rest of the CONO bits conflicts 
with these actions, the other bits have precedence. 



141 



§4.4 CARD PUNCH 

21 If a card is currently being processed in the punch (Card in Punch, 

CONI bit 27, is 1> or was ejected less than 3 ms ago, offset it when it 
is placed in the stacker. The card will actually stick out about a half 
inch from the rest of the stacked deck. 

23 If a card is currently being processed (Card in Punch, CONI bit 27, 
is 1 ), punch whatever data is in the 4-column buffer and then eject 
the card. Ejection moves a card through the punch head assembly 
four times as fast as punching blank columns. 



4-19 

With the console model, off- 
setting a card places it in a 
separate stacker. 



CONI CDP, 



Conditions In, Card Punch 



71124 


/ 


X 


Y 



12 13 14 17 11 



35 



Read the status of the punch into the right half of location E as shown. 









NEED 

OPERATOR 

SERVICE 

/ 




* 


TROUBLE 

INTERRUPT 

ENABLED 

r— /-. 






* 






* 




TEST 




HOPPER 
LO* 


/ 


PICK 

FAILURE- 
STACK 

FAILURE 


EJECT 

FAILURE 


TROUBLE 


/ 


ERROR 


CARD 

IN 
PUNCH 


ENO 
OF 

CARD 
ENABLED 


END 
OF 
CARD 


PUNCH 
ON 


BUSY 


DATA 
REQUEST 


PRIORITY 

INTERRUPT 

ASSIGNMENT 

1 1 


18 


19 


20 


21 


22 


23 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 34 35 



Notes. 

Interrupts are requested on the assigned channel by the setting of Data 
Request, End of Card, and if enabled, Trouble. 

1 8 The operator has turned on the test switch, taking the punch off hne. 

20 Less than a hundred cards are left in the hopper. 

V 

21 The hopper is empty or the stacker or chip box is full. 

22 The punch has received data for the first column but has failed to 
bring in a card from the hopper; or it has received an eject command 
but has failed to place the card properly in the stacker. 

23 The punch has received an eject command but has failed to move the 
card out of the punch head assembly. 

24 Bit 18, 22 or 23 is 1, or bit 2 1 is 1 because the hopper is empty or the 
stacker is full, or the operator has taken the punch off line. If bit 25 
is also 1 , the setting of Trouble requests an interrupt on the assigned 
channel. 

Ordinarily a trouble condition allows the punch to finish a card 
but prevents it from starting another; only a power failure or the op- 
erator turning on the test switch (bit 1 8) can take the punch off line 
in the middle of a card. A full chip box does not stop the punch at 
all as there is actually enough room left for the chips from a whole 



♦These bits cause interrupts 



4-20 



142 

HARDCOPY EQUIPMENT 



§4.4 



hopper full of cards. Although a 1 in bit 24 does not necessarily im- 
ply a malfunction, it always requires operator intervention. If bit 21 
is 1 it is very likely that the only trouble is the hopper is «mpty or the 
stacker is full. 

26 A column punched in a card does not agree with the data sent by the 
processor. 

27 A card is in the punch head assembly. The program can give a CONO 
offset or eject command while this bit is 1 (the offset can also be 
given within 3 ms after Card in Punch clears). 

29 Bit 28 is 1 and the program has given either an eject command or data 
for column 80. The setting of End of Card requests an interrupt on 
the assigned channel. 



OATAO COP, 



Data Out Card Punch 



7 1114 


/ 


X 


Y 



12 13 14 



17 IJ 



35 



Clear Data Request, set Punch On and Busy, and load the contents of bits 
24-35 of location E into the interface column buffer where the correspond- 
ence of bit positions to card rows is as shown. 



1 ROW 12 


ROW 11 


ROWO 


ROW 1 


ROW 2 


ROW 3 


ROW 4 


ROWS 


ROW 6 


ROW 7 


ROWS 


ROW 9 


24 


25 


26 


27 


28 


29 


30 


31 


32 


33 


34 


35 



If the program gives a DATAO 
to turn on the motor, the ini- 
tial ready from the punch 
takes the first column from 
the column buffer but does 
not set Data Request. When 
that flag does set, the punch is 
ready for the second column. 



Setting Punch On turns on the punch motor, but only a DATAO can pick 
a card. Since DATAO also sets Punch On, the program can initiate punch 
operations while supplying data, but the usual procedure is to set Punch On 
while giving other ihitial conditions. 

When the punch is ready to take a card from the hopper it sends a ready 
signal to the interface. This sets Data Request, which requests an interrupt 
on the assigned channel. To pick a card the program must respond with a 
DATAO, which supplies the first column, clears Data Request, and sets Punch 
On and Busy. The interface then sends the column to the 4-column punch 
buffer and clears Busy. While the punch is picking a card it also makes three 
more data requests to each of which the program must respond with a 
DATAO. Whqn the card is properly registered in the punch head assembly, 
Card in Punch sets. When this flag has set and the program has supplied the 
first four columns, the device punches the four columns simultaneously (a 1 
sent to the column buffer produces a hole in the card). The punch then con- 
tinues in this fashion making four data requests for each set of four columns. 

Punch On clears when the program gives an eject command. This causes 
,the device to punch whatever is in its 4-column buffer and the card then 



§4.4 



143 

CARD PUNCH 



4-21 



moves out to the stacker. If the punch has already sent a ready signal, the 
CONO that ejects should also clear Data Request. If End of Card has been 
enabled by a 1 in CONO bit 28, the eject command sets it, requesting an in- 
terrupt. If no eject command has been given by the time data is supplied for 
column 80, End of Card sets anyway if it is enabled (producing an interrupt 
request), but the card remains in the punch head assembly until an eject com- 
mand is given. The actual ejection of a card clears Card in Punch. 

Timing. If Punch On is set when the punch motor is off, the first ready 
signal is delayed about 1 20 ms while the motor gets up to speed. When the 
motor is on, Card in Punch sets about 60 ms after the DATAO that sends the 
first column for a card. While the card is in the head assembly, punching is 
synchronized to a punch cycle of 1 1 . 1 ms. About 30 /is elapse from each 
DATAO to the next Data Request, but after the first request the program 
has the full punch cycle time to supply all four columns and keep punching 
at^the maximum rate; after that punching is delayed until the next cycle. 

Giving an eject command clears Punch On and sets End of Card after 5 /lis, 
but Card in Punch does not clear until the card leaves the head assembly; this 
takes about 25 ms plus 2.8 ms for each set of four columns skipped over. 
After Card in Punch clears, about 30 us elapse before the punch indicates 
that it is ready to pick another card from the hopper, at which time the pro- 
gram should give a DATAO to pick another card at the maximum rate. (Of 
course the first DATAO can be given right after the eject command, and the 
punch will then pick another card automatically without setting Data Re- 
quest for the first column.) When the final card is punched, the hopper 
empty signal is simultaneous with End of Card. If Punch On remains clear 
for about 30 seconds, the motor turns off. 

Operation. The punch has a 
hopper and stacker capacity of 

1000 cards. To load the hop- __ „ , 

per, first fan the cards and jog 
them on the punch shelf. Turn 
the deck over and put the first 
hundred cards (about an inch 
of the deck) into the hopper 
(upper right) with the 9 edge 
against the back so column 1 is 
punched first. Hold the right 
end higher so the leading edge 
of the bottom card rests against 
the picker throat, and drop the 
cards in place. Put the rest of 
the deck on top of the first 
part. Cards can be added to 
the hopper while the punch is 
running, but always stop the 
punch before removing cards 
from the stacker. To remove 
cards, push down the elevator 
and lift the stack out. 



If the program does not eject 
before the punch starts punch- 
ing columns 77- 80, it makes 
another data request. The 
program can then supply two 
more colunuis, which will be 
punched in the margin of the 
card. 



Caution 

Any data that is given but 
not punched (eg the first col- 
umn(s) when there is a pick 
failure) is usually lost when 
the punch goes off line. Hence 
the program should always 
start with the first column of 
a card when the punch is re- 
started. 




Card Punch 



144 

HARDCOPY EQUIPMENT §4 4 

The punch is operated by the buttons in the upper part of the panel at the 
right. The alternate-action POWER switch lights green when power is on. 
Pushing START places the punch on line so the program can punch cards. 
The OPERATE indicator at the lower right hghts green when the punch mo- 
tor is up to speed. Pushing STOP takes the reader off line but does not stop 
the motor; the motor is turned off only by pressing CLEAR. 

The Ughts in the bottom row indicate an empty hopper or full stacker, a 
full chip box, a pick failure, an eject failure, and a stack failure. When one of 
these hghts other than CHIP BOX goes on, the STOP light also goes on (the 
punch always finishes the current card before stopping). If any trouble Ught 
remains on after the problem is corrected, press the CLEAR button; this turns 
off both the lights and the corresponding status signals read by a CONI. Press- 
ing CLEAR also ejects a card if one is in the head assembly, and the button 
glows red when clear action is required (eg when a card has gotten stuck). For 
a pick failure, empty the hopper, throw out the bottom card, and reload. 
Press START to allow the program to continue punching. If the trouble per- 
sists enter it in the system log and notify maintenance personnel. 

A full chip box does not stop the punch, but once it has been stopped by 
some other condition (such as an empty hopper), pressing START will not 
place the unit on line until the box has been emptied. 

At the right is a light for the Card in Punch flag. The ERROR light dis- 
plays the signal that sets the Error flag; it goes off when CLEAR is pressed. 
The CHECKOFF light is not used. When the TEST light is on, the device 
punches cards off hne in a test pattern (the test switch is behind the panel 
under the shelO- 

Lights for the interface are in the second row from the bottom on the hard- 
copy control indicator panel [page 4-9] . The middle section of the row dis- 
plays the contents of the card column buffer; the Ughts are marked by card 
row. Among the hghts in the right section, PI REQ is on while an interrupt 
is being requested whatever the cause. The remaining lights display some of 
the status conditions read by a CONI. 

Also available is a console model punch that has a 2000-card hopper and 
two 2000-card stackers. In use it differs from the compact model only in 
that offsetting a card places it in the second stacker (the one on the right), 
and cards can be removed from the stackers while the punch is running. 



145 



Appendices 



146 



147 



APPENDIX A 



INSTRUCTION AND DEVICE MNEMONICS 



The illustration on the next page shows the derivation of the instruction 
mnemonics. The two tables following it list all instruction mnemonics and 
their octal codes both numerically and alphabetically. When two mnemonics 
are given for the same octal code, the first is the preferred form, but the 
assembler does recognize the second. For completeness, UUOs are listed for 
user mode (an asterisk indicates a UUO mnemonic recognized by Macro for 
communication with the PDF- 10 Time Sharing Monitor). All UUOs 
000-077 are identical when the processor is not in user mode. 

In-out device codes are included only in the alphabetic hsting and are 
indicated by a dagger (f). Following the tables is a chart that hsts the 
devices with their mnemonic and octal codes and DEC option numbers for 
both PDP-10 and PDP-6. A device mnemonic ending in the numeral 2 is 
the recommended form for the second of a given device, but such codes are 
not recognized by Macro - they must be defined by the user. 



Al 



A2 



148 

MNEMONICS 



MOV 



E 

e Negative 
e Magnitude 
e Swapped 



Half word 



JRightl (Rightl 



iLeft r^lLeft | 



no effect 
Ones 

Zeros 
Extend sign 



to AC 

Immediate to ac 
to Memory 
to Self 



BLock Transfer 
EXCHange ac and memory 



use present pointer) , j LoaD Byte into ac 
Increment pointer | I DePosit Byte in memory 



Increment pointer | 
Increment Byte Pointer 



PUSH down 
POP up 



II 



and Jump 



SETto< 



Zeros 

Ones 

Ac 

Memory 

Complement of Ac 

Complement of Memory ^ 



AND I 

inclusive OR ) 

Inclusive OR 
exclusive OR 

EQuiValence 



with Complement of Ac 
with Complement of Memory 
Complements of Both 



■to 



AC 

AC Immediate 

Memory 

Both 



SKIP if memory I 
JUMP if AC 1 

Add One to 
Subtract One from 



II 



memory and Skipl 
AC and Jump ( 

^ A (Immediate \ ^ , . .^ 

Compare Ac \^.^^ j^^^^^j and skip if ac 



if--^ 



never 
Less 
Equal 

Less or Equal 
Always 
Greater 

Greater or Equal 
, Not equal 



Add One to Both halves of ac and Jump if j j^f ^^^^^^ 

I Negative 



Test AC 



with Direct mask 
with Swapped mask 
Right with E 
Left with E 



ADD 

SUBtract 
MULtiply 
Integer MULtiply 
Divide 
Integer DIVide 



rand Round- 



Floating AdD 
Floating SuBtract 
Floating MultiPly 
Floating DiVide 

Floating SCale 

Double Floating Negate 

Unnormalized Floating Add 



Immediate 
to Memory 
to Both 

Long 

to Memory 

to Both 



Arithmetic SHift 
Logical SHift 
ROTate 



|l 



Combined 



Jump-< 



to Sub Routine 

and Save Pc 

and Save Ac 

and Restore Ac 

if Find First One 

on Flag and CLear it 

on overflow (JFCL 10,) 

on CaRrY (JFCL 4,) 

on CaRrY 1 (JFCL 2,) 

on CaRrY (JFCL 6,) 

on Floating overflow (JFCL 1,) 

and ReSTore 

and ReSTore Flags (JRST 2,) 

and ENable PI channel (JRST 12,) 

HALT (JRST 4,) 

eXeCuTe 



DATAl 

BLocKJ I (in 

iitions-T '*^^ 

I . J ci • r I all masked bits Zero 
L-in and Skip if { , j , . ^ 

[ some masked bit On 



CONditions- 



One 



No modification 
set masked bits to Zeros 
set masked bits to Ones 
Complement masked bits, 



and skip 



never 

if all masked bits Equal 

if Not all masked bits equal 

Always 



149 



NUMERIC LISTING 



A3 



INSTRUCTION MNEMONICS 
NUMERIC LISTING 



000 


ILLEGAL 


132 


FSC 


001 




133 


IBP 




USER 


134 


ILDB 


■ 


UUO'S 


135 


LDB 


037- 




136 


IDPB 


040 


*CALL 


137 


DPB 


041 


*INIT 


140 


FAD 


042^ 




141 


FADE 


043 


RESERVED 


142 


FADM 


044 


FOR 
SPECIAL 


143 


FADB 


045 


MONITORS 


144 


FADR 


046, 




145 


FADRI 


047 


*CALLI 


146 


FADRM 


050 


*OPEN 


147 


FADRB 


051 


*TTCALL A 


150 


FSB 


052 




151 


FSBL 


053 


RESERVED 
FOR DEC 


152 


FSBM 


054] 




153 


FSBB 


055 


*RENAME 


154 


FSBR 


056 


*IN 


155 


FSBRI 


057 


*OUT 


156 


FSBRM 


060 


*SETSTS 


157 


FSBRB 


061 


*STATO 


160 


FMP 


062 


*STATUS 


161 


FMPL 


062 


*GETSTS 


162 


FMPM 


063 


*STATZ 


163 


FMPB 


064 


*INBUF 


164 


FMPR 


065 


*OUTBUF 


165 


FMPRI 


066 


*INPUT 


166 


FMPRM 


067 


*OUTPUT 


167 


FMPRB 


070 


*CLOSE 


170 


FDV 


071 


*RELEAS 


171 


FDVL 


072 


*MTAPE 


172 


FDVM 


073 


*UGETF 


173 


FDVB 


074 


*USETI 


174 


FDVR 


075 


*USETO 


175 


FDVRI 


076 


*LOOKUP 


176 


FDVRM 


077 


*ENTER 


177 


FDVRB 


100 




200 


MOVE 




UNASSIGNED 


201 


MOVEI 




CODES 


202 


MOVEM 


127 . 




203 


MOVES 


130 


UFA 


204 


MOVS 


131 


DFN 


205 


MOVSI 



206 


MOVSM 


207 


MOVSS 


210 


MOVN 


211 


MOVNI 


212 . 


MOVNM 


213 


MOVNS 


214 


MOVM 


215 


MOVMI 


216 


MOVMM 


217 


MOVMS 


220 


IMUL 


221 


IMULI 


222 


IMULM 


223 


IMULB 


224 


MUL 


225 


MULI 


226 


MULM 


227 


MULB 


230 


IDIV 


231 


IDIVI 


232 


IDIVM 


233 


IDIVB 


234 


DIV 


235 


DIVI 


236 


DIVM 


237 


DIVB 


240 


ASH 


241 


ROT 


242 


LSH 


243 


JFFO 


244 


ASHC 


245 


ROTC 


246 


LSHC 


247 




250 


EXCH 


251 


BET 


252 


AOBJP 


253 


AOBJN 


254 


JRST 


25410 


JRSTF 


25420 


HALT 


25450 


JEN 


255 


JFCL 


25504 


JFOV 



150 



A4 



25510 


JCRYl 


25520 


JCRYO 


25530 


JCRY 


25540 


JOV 


256 


XCT 


257 




260 


PUSHJ 


261 


PUSH 


262 


POP 


263 


POPJ 


264 


JSR 


265 


JSP 


266 


JSA 


267 


JRA 


270 


ADD 


271 


ADDI 


272 


ADDM 


273 


ADDB 


274 


SUB 


275 


SUBI 


276 


SUBM 


277 


SUBB 


300 


CAI 


301 


CAIL 


302 


CAIE 


303 


CAILE 


304 


CAIA 


305 


CAIGE 


306 


CAIN 


307 


CAIG 


310 


CAM 


311 


CAML 


312 


CAME 


313 


CAMLE 


314 


CAMA 


315 


CAMGE 


316 


CAMk 


317 


CAMG 


320 


JUMP 


32] 


JUMPL 


321 


JUMPE 


323 


JUMPLE 


324 


JUMPA 


325 


JUMPGE 


326 


JUMPN 


327 


JUMPG 


330 


SKIP 


331 


SKIPL 


332 


SKIPE 





MNEMONICS 


333 


SKIPLE 


334 


SKIPA 


335 


SKIPGE 


336 


SKIPN 


337 


SKIPG 


340 


AOJ 


341 


AOJL 


342 


AOJE 


343 


AOJLE 


344 


AOJA 


345 


AOJGE 


346 


AOJN 


347 


AOJG 


350 


AGS 


351 


AOSL 


352 


AOSE 


353 


AOSLE 


354 


AOSA 


355 


AOSGE 


356 


AOSN 


357 


AOSG 


360 


SOJ 


361 


SOJL 


362 


SOJE 


363 


SOJLE 


364 


SOJA 


365 


SOJGE 


366 


SOJN 


367 


SOJG 


370 


SOS 


371 


SOSL 


372 


SOSE 


373 


SOSLE 


374 


SOSA 


375 


SOSGE ^ 


376 


SOSN 


377 


SOSG 


400 


SETZ 


400 


CLEAR 


401 


SETZI 


401 


CLEARI 


402 


SETZM 


402 


CLEARM 


403 


SETZB 


403 


CLEARB 


404 


AND 


405 


AND! 


406 


ANDM 


407 


ANDB 



410 
411 
412 
413 
414 
415 
416 
417 
420 
421 
422 
423 
424 
425 
426 
427 
430 
431 
432 
433 
434 
434 
435 
435 
436 
436 
437 
437 
440 
441 
442 
443 
444 
445 
446 
447 
450 
451 
452 
453 
454 
455 
456 
457 
460 
461 
462 
463 
464 



ANDCA 

ANDCAI 

ANDCAM 

ANDCAB 

SETM 

SETMI 

SETMM 

SETMB 

ANDCM 

ANDCMI 

ANDCMM 

ANDCMB 

SETA 

SETAI 

SETAM 

SETAB 

XOR 

XORI 

XORM 

XORB 

lOR 

OR 

lORI 

ORI 

lORM 

ORM 

lORB 

ORB 

ANDCB 

ANDCBI 

ANDCBM 

ANDCBB 

EQV 

EQVI 

EQVM 

EQVB 

SETCA 

SETCAI 

SETCAM 

SETCAB 

ORCA 

ORCAI 

ORCAM 

ORCAB 

SETCM 

SETCMI 

SETCMM 

SETCMB 

ORCM 



151 







NUMERIC LISTING 






465 


ORCMI 


546 


HLRM 


627 


TLZN 


466 


ORCMM 


547 


HLRS 


630 


TDZ 


467 


ORCMB 


550 


"HRRZ 


631 


TSZ 


470 


ORCB 


551 


HRRZI 


632 


TDZE 


471 


ORCBI 


552 


HRRZM 


633 


TSZE 


472 


ORCBM 


553 


HRRZS 


634 


TDZA 


473 


CRCBB 


554 


HLRZ 


635 


TSZA 


474 


SETO 


555 


HLRZI 


636 


TDZN 


475 


SETOI 


556, 


HLRZM 


637 


TSZN 


476 


SETOM 


557 


HLRZS 


640 


TRC 


477 


SETOB 


560 


HRRO 


641 


TEC 


500 


HLL 


561 


HRROI 


642 


TRCE 


501 


HLLI 


562 


HRROM 


643 


TECE 


502 


HLLM 


563 


HRROS 


644 


TRCA 


503 


HLLS 


564 


HLRO 


645 


TLCA 


504 


HRL 


565 


HLROI 


646 


TRCN 


505 


HRLI 


566 


HLROM 


647 


TLCN 


506 


HRLM 


567 


HLROS 


650 


TDC 


507 


HRLS 


570 


HRRE 


651 


TSC 


510 


HLLZ 


571 


HRREI 


652 


TDCE 


511 


HLLZI 


572 


HRREM 


653 


TSCE 


512 


HLLZM 


573 


HRRES 


654 


TDCA 


513 


HLLZS 


574 


HERE 


655 


TSCA 


514 


HRLZ 


575 


HLREI 


656 


TDCN 


515 


HRLZI 


576 


HLREM 


657 


TSCN 


516 


HRLZM 


577 


HLRES 


660 


TRO 


517 


HRLZS 


600 


TRN 


661 


TLO 


520 


HLLO 


601 


TEN 


662 


TROE 


521 


HLLOI 


602 


TRNE ^ 


663 


TLOE 


522 


HLLOM 


603 


TLNE 


664 


TROA 


523 


HLLOS 


604 


TRNA 


665 


TEOA 


524 


HRLO 


605 


TLNA 


666 


TRON 


525 


HRLOI 


606 


TRNN 


667 


TLON 


526 


HRLOM 


607 


TLNN 


670 


TDO 


527 


HRLOS 


610 


TDN 


671 


TSO 


530 


HLLE 


611 


TSN 


672 


TDOE 


531 


HLLEI 


612 


TDNE 


673 


TSOE 


532 


HLLEM 


613 


TSNE 


674 


TDOA 


533 


HLLES 


614 


TDNA 


675 


TSOA 


534 


HRLE 


615 


TSNA 


676 


TDON 


535 


HRLEI 


616 


TDNN 


677 


TSON 


536 


HRLEM 


617 


TSNN 


70000 


BEKI 


537 


HRLES 


620 


TRZ 


70004 


DATAI 


540 


HRR 


621 


TLZ 


70004 


RSW 


541 


HRRI 


622 


TRZE 


70010 


BEKO 


542 


HRRM 


623 


TLZE 


70014 


DATAO 


543 


HRRS 


624 


TRZA 


70020 


CONO 


544 


HLR 


625 


TLZA 


70024 


CONI 


545 


HLRI 


626 


TRZN 


70030 
70034 


CONSZ 
CONSO 



A^ 



152 



A6 



MNEMONICS 



INSTRUCTION MNEMONICS 
ALPHABETIC LISTING 



tADC 


024 


BL" 
CA 


251 


DIVM 


236 


ADD 


270 


300 


tDLS 


240 


ADDB 


273 


GAIA 


304 


DPB 


137 


ADDI 


271 


CAIE 


302 


A tDPC 


250 


ADDM 


272 


CAIG 


307 


tDSK 


170 


AND 


404 


CATGE 


305 


tDTC 


320 


ANDB 


407 


CAIT 


301 


tDTS 


324 


ANDCA 


410 


CAILE 


303 


*ENTER 


077 


ANDCAB 


413 


CAIN 


306 


EQV 


444 


ANDCAI 


411 


*CALL 
*CALLI 


040 


EQVB 


447 


ANDCAM 


412 . 


047 


EQVI 


445 


ANDCB 


440 


CAM 


310 


EQVM 


446 


ANDCBB 


443 


CAMA 


314 


EXCH 


250 


ANDCBI 


441 


CAME 


312 


FAD 


140 


ANDCBM 


442 


CAMG 


317 


FADB 


143 


ANDCM 


420 


CAMGE 


315 


FADE 


141 


ANDCMB 


423 


CAML 


311 


FADM 


142 


ANDCMI 


421 


CAMLE 


313 


FADR 


144 


ANDCMM 


422 


CAMN 


3}6 


FADRB 


147 


ANDI 


405 


tcci 


014 


FADRI 


145 


ANDM 


406 


tCDP 


110 


FADRM 


146 


AOBJN 


253 


tCDR 


114 


FDV 


170 


AOBJP 


252 


CLEAR 


400 


FDVB 


173 


AOJ 


340 


CLEARB 


403 


FDVL 


171 


AOJA 


344 


CLEAR! 


401 


FDVM 


172 


AOJE 


342 


CLEARM 


i^02 


FDVR 


174 


AOJG 


347 


*CLOSE 


070 


FDVRB 


177 


AOJGE 


345 


CONI 


70024 


FDVRl 


175 


AOJL 


341 


CONG 


70020 


FDVRM 


176 


AOJLE 


343 


CONSO 


70034 


FMP 


160 


AOJN 


346 


CONSZ 


70030 


FMPB 


163 


AGS 


350 


tCPA 


000 


FMPL, 


161 


AOSA 


354 


tCR 


150 


FMPM 


162 


AOSE 


352 


DAxil 


70004 


j FMP|l 


164 


AOSG 


357 


DATAO 


70014 


1 FMPRB 


167 


AOSGE 


355 


tDC 


200 


FMPRI 


165 


AOSL 


351 


fDCSA 


300 


FMPRM 


166 


AOSLE 


353 


tDCSB 


304 


FSB 


150 


AOSN 


356 


tDF 


270 


FSBB 


153 


tAPR 


000 


DFN 


131 


FSBL 


151 


ASH 


240 


tDIS 


130 


fsbM 


152 


ASHC 


244 


DIV 


234 


FSBR 


154 


BLKI 


70000 


DIVB 


237 


FSBRB 


157 


BLKO 


70010 


qivi 


235 


FSBRI 


155 



153 



ALPHABETIC LISTING 



A7 



FSBRM 


156 


HRLZI 


515 


JSA 


266 


FSC 


132 


HRLZM 


516 


JSP 


265 


'GETSTS 


062 


HRLZS 


517 


JSR 


'264 


HALT 


25420 


HRR 


540 


JUMP 


320 


HLL 


500 


HRRE 


570 


JUMPA 


324 


HLLE 


530 


HRREI 


571 


JUMPE 


322 


HLLEI 


531 


HRREM 


572 


JUMPG 


,327 


HLLEM 


532 


HRRES 


573 


JUMPGE 


325 


HLLES 


533 • 


HRRI 


541 


JUMPL 


321 


HLLI 


501 


HRRM 


542 


JUMPLE 


323 


HLLM 


502 


HRRO 


560 


JUMPN 


326 


HLLO 


520 


HRROI 


561 


LDB 


135 


HLLOI 


521 


HRROM 


562 


*LOOKUP 


076 


HLLOM 


522 


HRROS 


563 


tLPT 


124 


HLLOS 


523 


HRRS 


543 


LSH 


242 


HLLS 


503 


HRRZ 


550 


LSHC 


246 


HLLZ 


510 


HRRZI 


551 


tMDF 


260 


HLLZI 


511 


HRRZM 


552 


MOVE 


200 


HLLZM 


512 


HRRZS 


553 


MOVEI 


201 


HLLZS 


513 


IBP 


133 


MOVEM 


202 


HLR 


544 


IDIV 


230 


MOVES 


203 


HERE 


574 


IDIVB 


233 


MOVM 


214 


HLREI 


575 


IDIVI 


231 


MOVMI 


215 


HLREM 


576 


IDIVM 


232 


MOVMM 


216 


HLRES 


577 


IDPB 


136 


MOVMS 


217 


HLRI 


545 


ILDB 


134 


MOVN 


210 


HLRM 


546 


IMUL 


220 


MOVNI 


211 


HLRO 


564 


IMULB 


223 


MOVNM 


212 


HLROI 


565 


IMULI 


221 


MOVNS 


213 


HLROM 


566 


IMULM 


222 


MOVS 


204 


HLROS 


567 


*IN 


056 


MOVSI 


205 


HLRS 


547 


*INBUF 


064 


MOVSM 


206 


HLRZ 


554 


*INIT 


041 


MOVSS 


207 


HLRZI 


555 


*INPUT 


066 


*MTAPE 


072 


HLRZM 


556 


lOR 


434 


tMTC 


220 


HLRZS 


557 


lORB 


437 


tMTM 


230 


HRL 


504 


lORI 


435 


tMTS 


224 


HRLE 


534 


lORM 


436 


MUL 


224 


HRLEI 


535 


JCRY 


25530 


MULB 


227 


HRLEM 


536 


JCRYO 


25520 


MULI 


225 


HRLES 


537 


JCRYl 


' 25510 


MULM 


226 


HRLI 


505 


JEN 


25460 


*OPEN 


050 


HRLM 


506 


JFCL 


255 


OR 


434 


HRLO 


524 


JFFO 


243 


ORB 


437 


HRLOI 


525 


JFOV 


25504 


ORCA 


454 


HRLOM 


526 


JOV 


25540 


ORCAB 


457 


HRLOS 


527 


JRA 


267 


ORCAI 


455 


HRLS 


507 


JRST 


254 


ORCAM 


456 


HRLZ 


514 


JRSTF 


25410 


ORCB 


470 



154 



A8 



ORCBB 


473 


ORCBI 


471 


ORCBM 


472 


ORCM 


464 


ORCMB 


467 


ORCMI 


465 


ORCMM 


466 


ORI 


435 


ORM 


436 


*OUT 


057 


*OUTBUF 


065 


*OUTPUT 


067. 


tPI 


004 


tPLT 


140 


POP 


262 


POPJ 


263 


tPTP 


100 


tPTR 


104 


PUSH 


261 


PUSHJ 


260 


*RELEAS 


071 


♦RENAME 


055 


ROT 


241 


ROTC 


245 


RSW 


70004 


SETA 


424 


SETAB 


427 


SETAI 


425 


SETAM 


426 


SETCA 


450. 


SETCAB 


453 


SETCAI 


451 


SETCAM 


452 


SETCM 


460 


SETCMB 


463 


SETCMI 


461 


SETCMM 


462 


SETM 


414 


SETMB 


417 


SETMI 


415 


SETMM 


416 


SETO 


474 


SETOB 


477 


SETOI 


475 


SETOM 


476 


*SETSTS 


060 


SETZ 


400 


SETZB 


403 


SETZI 


401 



MNEMONICS 


SETZM 


402 


SKIP 


330 


SKIPA 


334 


SKIPE 


332 


SKIPG 


337 


SKIPGE 


335 


SKIPL 


331 


SKIPLI 


333 


SKIPN 


336 


SOJ 


360 


SOJA 


364 


SOJE 


362 


SOJG 


367 


SOJGE 


365 


SOIL 


361 


SOJLE 


363 


SOJN 


366 


SOS 


370 


SOSA 


374 


SOSE 


372 


SOSG 


377 


SOSGE 


375 


SOSL 


371 


SOSLE 


373 


SOSN 


376 


*STATO 


061 


♦STATUS 


062 


*STATZ 


063 


SUB 


274 


SUBB 


277 


SUBI 


275 


SUBM 


276 


TDC 


650 


TDCA 


654 


TDCE 


652 


TDCN 


656 


TDN 


610 


TDNA 


614 


TDNE 


612 


TDNN 


616 


TDO 


670 


TDOA 


674 


TDOE 


'672 


TDON 


676 


TDZ 


630 


TDZA 


634 


TDZE 


632 


TDZN 


636 


TLC 


641 



TLCA 


645 


TLCE 


643 


TLCN 


647 


TLN 


601 


TLNA 


605 


TLNE 


603 


TLNN 


607 


TLO 


661 


TLOA 


665 


TLOE 


663 


TLON 


667 


TLZ 


621 


TLZA 


625 


TLZE 


623 


TLZN 


.627 


TMC 


340 


TMS 


344 


TRC 


640 


TRCA 


644 


TRCE 


642 


TRCN 


646 


TRN 


600 


TRNA 


604 


TRNE 


602 


TRNN 


606 


TRO 


660 


TROA 


664 


TROE 


662 


TRON 


666 


TRZ 


620 


TRZA 


624 


TRZE 


622 


TRZN 


626 


TSC 


651 


TSCA 


65 S 


TSCE 


653 


TSCN 


657 


TSN 


611 


TSNA 


615 


TSNE 


613 


TSNN 


617 


TSO 


671 


TSOA 


675 


TSOE 


673 


TSON 


677 


TSZ 


'631 


TSZA 


635 


TSZE 


633 


TSZN 


637 



*TTCALL 051 

UFA 130 

*UGETF 073 

*USETI 074 



155 




ALPHABETIC LISTING 


*USETO 


075 


tUTC 


210 


tUTS 


214 


XCT 


256 



A9 



XOR 


430 


XORB 


433 


XORI 


431 


XORM 


432 



156 



AlO 



MNEMONICS 



R 


















g 




e ^ 

en - 
o < 

o ^ 


Q 


















O 












O 




Q. U. 

u> 


o 












s 




2 2 


^ si? 

2 "^ 


2 


o 

z 


o 

UJ 

z 
o 










s 




o q: 




o 










? 




o 

2 


g 
2 °is 


o 

2 


cr> 

o 

1- 


Q. 

o 

z 

z 










§ 




o 

2 


O 


2 










s 




oo 

o Q o 
«,'2 




2 


CVJ 

CM 
O 


1 

o 

LU 

a 










o 

ro 


° So: 

S cvj ^te 
s 1" 


o o 


to 

111 


2 










Si 


2 aa: 


«>o (t 


a. 


o 
o 


Q 


LlJ 

o 










s 


s ii 




O 

•— 










2: 


i -s 

Hi 


3 


CO 

ID 












o 


5 § 


O Q_ Z 
O '^ 

o g 

2 5 


(J 

UJ 

1- 
=> 
to 












o 


^1 


«,2 ^ 


" CVJ «g 


o 

ID 


OD 
CO 

o 

o 


o 

z 

i 

o 

o 










z2e X 






o 
<o 


lO 











o. a. -8 2 

o & S^ 

^ w '5 o 

till 



r/ 



z "" 


2 


ml 


<n 


go 
o 


OD 

<o 


t _ 

o 
o:_i 

o 

o — 




- 


CVJ 


- 


- 


^ 


o 



U-OO 



, ro 



CO 



S30IA3a QdVONViS 030 



S33IA3a lVID3dS a3sn 



157 



APPENDIX B 



INPUT-OUTPUT CODES 



The table beginning on the ne;tt page lists the completje teletype code. The 
lower case character set (codes 140-176) is not available on the Model 35, 
but giving one of these codes causes the teletype to print the corresponding 
upper case character. Other differences between the 35 and 37 are men- 
tioned in the table. The definitions of the control codes are those given by 
ASCII. Most control codes, however, have no effect on the console teletype, 
and the definitions bear no necessary relation to the use of the codes in con- 
junction with the PDP-10 software. 

The Ime printer has the same codes and characters as the teletype. The 
64-character printer has the figure and upper case sets, codes 040-137 
(again, giving a lower case code prints the upper case character). The "96"- 
character printer has these plus the lower case set, codes 040-176. The 
latter printer actually has only ninety-five characters unless a special charac- 
ter is "hidden" under the delete code, 177. A hidden character is printed by 
sending its code prefixed by the delete code. Hence a character hidden under 
DEL is printed by sending the printer two 1 77s in a row. 

Besides printing characters, the line printer responds to ten control charac- 
ters, HT, CR, LF, VT, FF, DLE and DCl -4. The 128-character printer uses 
the entire set of 7-bit codes for printable characters, with characters hidden 
under the ten control characters that affect the printer and also under null 
and delete. In all cases, prefixing DEL causes the hidden character to be 
printed. The extra thirty-three characters that complete the set are ordered 
special for each installation. 

The first page of the table of card codes [pages B6~8] lists the column 
punch required to represent any character in the two DEC codes. The octal 
codes listed are those used by the PDP-10 software.. In other words, when 
reading cards, the Monitor translates the column punch into the octal code 
shown; when punching cards, it pro4uces the listed column punch when 
given the corresponding code. The remaining pages of the table show the 
relationship between the DEC card codes and several IBM card punches. 
Each of the column punches is produced by a single key on any punch for 
which a character is listed, the character being that which is printed at the 
top of the card. 



158 

B2 INPUT-OUTPUT CODES 

TELETYPE CODE 



Even 
Parity 


7-Bit 
Octal 




Bit 


Code 


Character 





000 


NUL 


1 


001 


SOH 


1 


002 


STX 





003 


ETX 


1 


004 


EOT 





005 


ENQ 





006 


ACK 


1 


007 


BEL 


1 


010 


BS 





Oil 


HT 





012 


LF 


1 


013 


VT 





014 


FF 


1 


015 


CR 


1 


016 


SO 





017 


SI 


1 


020 


DLE 





021 


DCl 





022 


DC2 


1 


023 


DC3 





024 


DC4 


1 


025 


NAK 


1 


026 


SYN 





027 


ETB 





030 


CAN 


1 


031 


EM 


1 


032 


SUB 





033 


ESC 


1 


034 


FS 





035 


GS 



Remarks 

Null, tape feed. Repeats on Model 37. Control shift P on Model 35. 

Start of heading; also SOM, start of message. Control A. 

Start of text; also EOA, end of address. Control B. 

End of text; also EOM, end of message. Control C. 

End of transmission (END); shuts off TWX machines. Control D. 

Enquiry (ENQRY); also WRU, "Who are you?" Triggers identification 

("Here is . . . '*) at remote station if so equipped. Control E. 

Acknowledge; also RU, "Are you . . . ?" Control F. 

Rings the bell. Control G. 

Backspace; also FEO, format effector. Backspaces some machines. 

Repeats on Model 37. Control H on Model 35. 

Horizontal tab. Control I on Model 35. 

Line feed or line space (NEW LINE); advances paper to next line. Repeats 

on Model 37. Duplicated by control J on Model 35. 

Vertical tab (VTAB). Control K on Model 35. 

Form feed to top of next page (PAGE). Control L. 

Carriage return to beginning of line. Control M on Model 35. 

Shift out; changes ribbon color to red. Control N. 

Shift in; changes ribbon color to black. Control O. 

Data link escape. Control P (DCO). 

Device control 1 , turns transmitter (reader) on. Control Q (X ON). 

Device control 2, turns punch or auxiliary on. Control R (TAPE, 

AUX ON). 

Device control 3, turns transmitter (reader) off. Control S (X OFF). 

Device control 4, turns punch or auxiliary off. Control T ( TAPE , 

AUX OFF). 

Negative acknowledge; also ERR, error. Control U. 

Synchronous idle (SYNC). Control V. 

End of transmission block; also LEM, logical end of medium. Control W. 

Cancel (CANCL). Control X. 

End of medium. Control Y. 

Substitute. Control Z. 

Escape, prefix. This code is generated by control shift K on Model 35, 

but the Monitor translates it to 175. 

File separator. Control shift L on Model 35. 

Group separator. Control shift M on Model 35. 



Even 
Parity 


7-Bit 
Octal 




Bit 


Code 


Character 





036 


RS 




037 


US 




040 


SP 





041 


I 





042 


tt 




043 


# 





044 


$ 




045 


% 




046 


& 





047 


1 





050 


( 




051 


) 




052 


* 





053 


+ 




054 


> 





055 


~ 





056 


. 




057 


/ 





060 







061 


i 




062 


2 





063 


3 




064 


4 





065 


5 





066 


6 




067 


7 




070 


8 





071 


9 





072 


: 




073 


> 





074 


< 




075 


= 




076 


> 





077 


9 


1 


100 


@ 





101 


A 





102 


B 



159 

TELETYPE CODE B3 

Remarks 

Record separator. Control shift N on Model 35. 
Unit separator. Control shift O on Model 35. 
Space. 



Accent acute or apostrophe. 



Repeats on Model 37. 



Repeats on Model 37. 
Repeats on Model 37. 



Repeats on Model 37. 



B4 



160 

INPUT-OUTPUT CODES 



Even 
Parity 


7-Bit 
Octal 




Bit 


Code 


Character 


1 


103 


C 





104 


D 


1 


105 


E 


1 


106 


F 





107 


G 





110 


H 


1 


111 


I 


1 


112 


J 





113 


K 


1 


114 


L 





115 


M 





116 


N 


1 


117 


O 





120 


P 


1 


121 


Q 


1 


122 


R 





123 


S 


1 


124 


T 





125 


U 





126 


V 


1 


127 


w 


1 


130 


X 





131 


Y 





132 


z 


1 


133 


[ 





134 


\ 


1 


135 


] 


1 


136 


, t 





137 


^(r- 





140 


' 


1 


141 


a 


1 


142 


b 





143 


c 


1 


144 


d 





145 


e 





146 


f 


1 


147 


g 



Remarks 



Repeats on Model 37. 



Shift K on Model 35. 
Shift L on Model 35. 
Shift M on Model 35. 

Repeats on Model 37. 

Accent grave. 



161 

TELETYPE CODE 



B5 



Even 
Parity 


7-Bit 
Octal 




Bit 


Code 


Character 


1 


150 


h 





151 


i 





152 


J 


1 


153 


k 





154 


1 


1 


155 


m 


1 


156 


n 





157 


o 


1 


160 


P 





161 


q 





162 


r 


1 


163 


s 





164 


t 


1 


165 


u 


1 


166 


V 





167 


w 





170 


X 


1 


171 


y 


1 


172 


z 





173 


{ 


1 


174 


1 





175 


I 





176 





Remarks 



Repeats on Model 37. 



177 



DEL 



This code generated by ALT MODE on Model 35. 

This code generated by ESC key (if present) on= Model 35, but the 

Monitor translates it to 175. 

Delete, rub out. Repeats on Model 37. 



REPT 

PAPER ADVANCE 
LOCAL RETURN 
LOCLF 
LOCCR 

INTERRUPT, BREAK 
PROCEED, BRK RLS 
HERE IS 



Keys That Generate No Codes 

Model 35 only: causes any other key that is struck to repeat continuously 
until REPT is released. 

Model 37 local line feed. 

Model 37 local carriage return. 

Model 35 local Hne feed. 

Model 35 local carriage return. 

Opens the line (machine sends a continuous string of null characters). 

Break release (not applicable). 

Transmits predetermined 21 -character message. 



MAY 1968 











162 








B6 






INPUT-OUTPUT CODES 

CARD CODES 










PDP-10 








PDP-10 






Character 


ASCII 


DEC 029 


DEC 026 


Character 


ASCII 


DEC 029 


DEC 026 


Space 


040 


None 


None 


@ 


100 


8 4 


84 


\ 


041 


11 8 2 


12 SI 


A 


101 


12 1 


12 1 


*i 


042 


8 7 


08 5 


B 


102 


12 2 


12 2 


# 


043 


83 


086 


C 


103 


12 3 


12 3 


$ 


044 


11 83 


11 83 


D 


104 


124 


124 


% 


045 


084 


087 


E 


105 


12 5 


12 5 


& 


046 


12 


11 8 7 


F 


106 


12 6 


12 6 


I 


047 


8 5 


8 6 


G 


107 


12 7 


12 7 


( 


050 


12 8 5 


084 A 


H 


110 


12 8 


12 8 


) 


051 


11 8 5 


12 8 4 A 


I 


111 


12 9 


12 9 


* 


052 


11 84 


118 4 


J 


112 


11 1 


11 1 


+ 


053 


12 8 6 


12 


K 


113 


112 


11 2 


> 


054 


08 3 


08 3 


L 


114 


11 3 


11 3 


— 


055 


11 


11 


M 


115 


11 4 


11 4 


. 


056 


12 8 3 


12 8 3 


N 


116 


11 5 


11 5 


/ 


057 


1 


1 


O 


117 


11 6 


11 6 





060 








P 


120 


11 7 


11 7 


1 


061 


1 


1 


Q 


121 


11 8 


11 8 


2 


062 


2 


2 


R 


122 


11 9 


11 9 


3 


063 


3 


3 


S 


123 


02 


2 


4 


064 


4 


4 


T 


124 


03 


03 


5 


065 


5 


5 


U 


125 


04 


04 


6 


066 


6 


6 


V 


126 


05 


05 


7 


067 


7 


7 


W 


127 


06 


06 


8 


070 


8 


8 


X 


130 


07 


7 


9 


071 


9 


9 


Y 


131 


08 


8 




072 


82 


1 1 8 2 or 1 1 


Z 


132 


09 


9 


> 


073 


118 6 


8 2 


[ 


133 


12 8 2 


118 5 


< 


074 


12 8 4 


12 8 6 


\ 


134 


1187 


8 7. 


= 


075 


86 


83 


] 


135 


08 2 


12 8 5 


> 


076 


08 6 


1186 


t 


136 


12 8 7 


8 5 


7 


077 


08 7 


12 8 2 or 12 


^ 


137 


8 5 


8 2 


Binary 


7 9 














Mode Switch 


120 2 46 8 












End of File 


12 11 


1 













The octal codes given above are those generated by the Monitor from the column punches. The card 
reader interface actually supplies a direct binary equivalent of the column punch, as listed in the following 
two pages. 



MAY 1968 



163 









CARD CODES 






B7 


Column 








Column 






Punch 


Character 


Octal 




Punch 


Character 


Octal 


None 


Space 


0000 




129 


I 


4001 








1000 




11 1 


J 


2400 


1 


1 


0400 




11 2 


K 


2200 


2 


2 


0200 




11 3 


1 


2100 


3 


3 


0100 




11 4 


M 


2040 


4 


4 


0040 




11 5 


N 


2020 


5 


5 


0020 ' 




11 6 


O 


2010 


6 


6 


0010 




11 7 


: P 


2004 


7 


7 


0004 




'll 8 


Q 


2002 


8 


8 


0002 




11 9 


R 


2001 


9 


9 


0001 




1 


/ 


1400 


12 1 


A 


4400 




2 


S 


1200 


12 2 


B 


4200 




03 


T 


1100 


12 3 


C 


4100 




04 


U 


1040 


12 4 


D 


4040 




5 


V 


1020 


12 5 


E 


4020 




06 


w 


1010 


12 6 


F 


4010 




7 


X 


1004 


12 7 


G 


4004 




8 


Y 


1002 


12 8 


H 


4002 




9 


Z 


1001 


Column 


026 Data 


026 










Punch 


Processing 


Fortran 


029 


DEC 026 


DEC 029 


Octal 


12 


& 


+ 


& 


+ 


& 


4000 


11 


- 


- 


- 


- 


- 


2000 


12 








? 




5000 


11 








: 




3000 


82 






: 


^ 


: 


0202 


83 


# 


— 


# 


= 


# 


0102 


8 4 


@ 


- 


@ 


@ 


@ 


0042 


85 






' 


t 


' 


0022 


86 






= 


t 


= 


0012 


87 






" 


\ 


tt 


0006 


12 8 2 






<^ 


7 


[ 


4202 


12 8 3 




. 


. 






4102 


128 4 . 


n 


) 


< 


) 


< 


4042 


12 8 5 






( 


] 


( 


4022 


12 8 6 






+ 


< 


4- 


4012 









164 








B8 






INPUT-OUTPUT CODES 






Column 


026 Data 


026 










Punch 


Processing 


Fortran 


029 


DEC 026 


DEC 029 


Octal 


12 8 7 






1 


j 


t 


4006 


11 8 2 






! 


: 


f 


2202 


11 8 3 


$ . 


$ 


$ 


$ 


$ 


2102 


11 84 


4( 


* 


* 


* 


* 


2042 


11 8 5 . 






) 


[ 


) 


2022 


11 86 






) 


> 


) 


2012 


11 8 7 






n 


& 


\ 


2006 


08 * 






See note 


> 


] 


1202 


083 


J ■ 


y 


i 


> 


> 


1102 


084 


% 


( 


% 


( 


% 


1042 


08 5 






-«- 


ti 


^ 


1022 


08 6 






> 


# 


> 


1012 


08 7 






7 


% 


? 


1006 


12 11 1 








End of File 


End of File 


7400 


12 2 468 








Mode Switch 


Mode Switch 


5252 


7 9 • 








Binary 


Binary 


a-a:05 



Note: There is a single key for the 8 2 punch on the 029 but printing is suppressed. 

The Monitor translates the octal code for the 12 punch in DEC 026 to 4202 (which corresponds to a 
12 8 2 punch), and the code for 1 1 to 2202 (1 1 8 2). 



165 



APPENDIX C 



MISCELLANY 



Instruction Flow Simplified C2 

Word Formats C3 

instruction Timing Flow Chart C4 

In-out Device Bit Assignments C6 

Indicator Panels C8 

Powers of Two CIO 



Cl 



166 



C2 



MISCELLANY 




INSTRUCTION FLOW SIMPLIFIED 



167 

WORD FORMATS 

BASIC INSTRUCTIONS 



14 17 18 

IN-OUT INSTRUCTIONS 



9 10 12 13 14 



17 1{ 



OVERFLOW 


CARRY 



CARRY 
1 


FLOATING 
OVERFLOW 


BYTE 
INTERRUPT 


USER 


USER 
IN-OUT 






...J 




FLO* 


NO 
DIVIDE 



10 11 12 



17 18 



C3 



INSTRUCTION CODE 

(INCLUDING MODE) 


A,F 


I 


X 


Y 



1 1 1 

1 1 


DEVICE CODE 


INSTRUCTION 
CODE 


/ 


X 


Y 







PC WORD 






FLAGS 





PC 





12 


13 17 


18 




35 





BLT POINTER [XWO] 




SOURCE ADDRESS 


DESTINATION ADDRESS 



BLKI/BLKO POINTER, PUSHDOWN POINTER, DATA CHANNEL CONTROL WORD [lOWO] 


-WORD COUNT 


ADDRESS -1 



BYTE POINTER 



POSITION P 


1 

SIZE S 




7 


X 


Y 



11 12 13 14 



BYTE STOP 


lAGE 










BYTE 


NEXT BYTE 1 



35-/'-5-1 I'b-P lb-P*\ 

FIXED POINT OPERANDS 



BINARY NUMBER (TWOS COMPLEMENT) 



8 9 



FLOATING POINT OPERANDS 



1- 


EXCESS 128 EXPONENT 

(ONES COMPLEMENT) 


FRACTION (TWOS COMPLEMENT) 



LOW ORDER WORD IN DOUBLE LENGTH FLOATING POINT OPERANDS 



EXCESS 128 EXPONENT-27 
IN POSITIVE FORM 



LOW ORDER HALf '^'^ FRACTION (TWOS COMPLEMENT) 



WORD FORMATS 



C4 



168 

MISCELLANY 




INSTRUCTION TIMING 
FLOW CHART 



.17 -f •C.ll) 
'if IN uaCH MODE 



MCMORY READ 
ACCESS (CHART 1) 



^ 



NONE OF THESE 



MEMORY OPERAND 
READ/MODIFY 



FLOATING POINT 
IMMEOUTE 



.26+ •(.II) 
*W IN USER MODE 




s 




m 



OTHER IMMEOIATES 

OR NO 
MEMORY OPERAND 



5 




•(.II) 
^IF IN USER I 



MEMORY READ 
ACCESS (CHART I) 



INSTRUCTIONS THAT USE READ/MODIFY 

All Bcwiean In Memory and Both Modes Except SET2, SETA, SETCA, SETO 

ADDM, ADDS, SUBM, SUBB 

HRRM, HRLM, HLRM, HLLM and All Halt Words In Self Mode 

MOVES, MOVNS, MOVMS, MOVSS 

ILDB, IDPB (First Time Only) 

IBP, BLKI. BLKO, OFN, EXCH 

AOS, SOS in all modes 



10-01 tf 



169 

MISCELLANY 



C5 



INSTRUCTION EXECUTION 





'' 






BooiMn (mtpt ANOCA, ANOCB, ORCA. ORCBI, 
Half Wofdi (wMpt HLR, HLHI, HRL, HRLII, MOVE. 
MOVS. EXCH. JFCL, JRST, JSP, XCT, UUO 


.27 






ANDCA, ANOCB, ORCA, ORCB. HLR, HLRI, 
HRL, HRLI, JSR, JSA, JRA, Ttct dm 


.62 






MOVN, MOVM, ADO, SUB, AOBJP. AOBJN, 
CAM, CAI. SKIP, JUMP, AOJ, AOS, SOJ, SOS 


M 






PUSH, PUSHJ. POP, POPJ, DFN 


.80 






JFFO 


.80 


+ . 19 limas numbar of laading Ot mod 18 




BLT 


.69 


(+ .1 1 if Uiar) + mamory writa Kcass + .52 
If not dona ♦ .09 and go to C3 




IBP 


.38 


+ .26 if ovarilow word boundary 




LOB, OPB First timi 


.61 


+ . 15 par liH count Go to CI 




ILDB, (DPB FIrit timi 


.74 


) + .15 par wa count \ - , _, 
\ + .26ifoy.rflow ( ^"""^^ 




ILOB, LDB Second timi 


.45 


+ . 15 par pofition count 




lOPB, DPB SKond timt 


.95 


+ .15 par position count 




Shift group 


(:llia} •-— 




MUL 

AvtrtgiiKCiptMULI 


6.02 
8.36 


+.13 par transition 
(18 transitions for 2.34) 




IMUL 

AwagiKctptlMULI 


6.34 
7.51 


+ .1 3 pr transition 
(9 transitions for 1.171 




FMP 

AvtrtgtMCiptFMPRI 


6.39 
8.21 


+ .13 par transition 
(14 transitions for 1.82) 




Noli: lmtn«di«ti mod* multiplicition h« only half the avaraga numbar of tranatiow 




OIV.IDIV 


13.78 






FSC 


1.52 


+ .25 par shift to normaiiza 




FAD. UFA 
Avtraga 


2.38 
4.33 


(+.15parshifttounnormaliM 
\ + .25parshifttonormali7a 




FSB 


Sama 


IS FAD + .18 




Rounding (axcapt divida) only wtwn Klually dona 


+.96 






Long mod* laxcaptdividtl 


+.69 






FOVR. FDV (axcapt FDVU 


12.00 






FOVL with fitt ACi 


13.28 






FDVL without fan ACt 


12.32 


(+ . 1 1 if Usar) + mamory raad Kcaas + .89 




CONG. COI«l. CONSO. CONSZ, DATAO, DATAI 
CONO.CONI.OATACOATAI 
CONSO, CONSZ 


.12 
+2.69 
+2.90 


Than wait until 4.50 has panad sinca last hara 




BLKO.BLKI 


.60 


Than turn into DATAO, DATAI and go to C2 




f 








IMEMOMY WHITE 

Access (CHAirr ii 



S 



SCE MEMONY 

TIMINOCHANT 

ron CYCLE 

COMPLETION TIME 




.17+ *(ll> 
' IF IN USEK MODE 



[4] 



MEMORY TIMIN6 



MEMOirr 


MAI« 


MBit 


MBt« 


KMtC 


PNOCCSSOKS 


SMOLE 
OR MULTI 


SINGLE 


MULTI 


SINGLE 
(BUILT m) 


crcu 

RCAO ACCESS 
WHITE ACCESS 

MODIFY 
COMPLETION 


too 

.M 

.20 
.39 


l.»9 
.60 
.20 
.39 


ISS 

.70 

30 

t.20 


.21 
21 



Q DONE ^ 



.17+ "(.M) 
«• IF M UXM MOOC 



MEMORY WRtrC 
ACCESS (CHART I) 



s 



NOTES . 

MEMORY ACCESS TIMES INCLUDE 20 FEET OF 
CABLE DELAY. 

ALL TIMES :9% 



C6 



170 

MISCELLANY 



(j$Cl 



ill. 



Ill 



5el 



8« 



'4 






"ii 



J 



>s 



>! 



iii 



4$ 






3. 



k\ 



i 



J 



Q9? 



i~ 



II 



5^ 



ii 




171 



IN-OUT DEVICE BIT ASSIGNMENTS 



C7 




S^ 



i^^ 



\m 






5|| 



Pi 



Is! 



lis 



lis 



S| 



iiK 



iStf 



^1 



l^i 



^11 



^^^5 



K^§ 
^?| 



I? 



i!^ 



I 



^1 



^? 



^oi 



^8 



i65^ 






II 



ill 



'.,2 






41 

(MB) 






imi 






hi 



m 



s 



m 



m 



f^.lli 



a?.^ 

m 



^^! 



i 



^1 



P,^ 



II 



^ 



11 



11 



''^i 
ii 






.5 .^ 






^R5 



^e^ 



3?u^ 



i?^ 



•i^- 
^1?^ 



^Si 



W4 






m 



mm 



h5 



C8 



172 

MISCELLANY 



« 



ffl 



■:•-::*■ I 



m 

INDICATOR PANELS 



C9 




^i:^"i 



^ 



WyI 


s 


^^:m 




mM 


2^ 


"--\---y.:i 


o 




u 


kt'-^ 


o 


vK-S 


i-H 


^i^'iii 


PQ 




:§ 


"MM 


^ ^ 




tU 


::K':-S 


c 



174 

CIO MISCELLANY 



POWERS OF TWO 



2N ^ 2- 



1.0 
0.5 
0.25 
0.125 
0.062 5 
0.031 25 
0.015 625 
0.007 812 5 
0.003 906 25 
0.001 953 125 
0.000 976 562 5 
0.000 488 281 25 
0.000 244 140 625 
0.000 122 070 312 5 
0.000 061 035 156 25 
O.OOO 030 517 578 125 
0.000 015 258 789 062 5 
0.000 007 629 394 531 25 
0.000 003 814 697 265 625 
0.000 001 907 348 632 812 5 
0.000 000^953 674 316 406 25 
0.000 000 476 837 158 203 125 
0.000 000 238 418 579 101 562 5 
0.000 000 119 209 289 550 781 25 
0.000 000 059 604 644 775 390 625 
0.000 000 029 802 322 387 695 312 5 
0.000 000 014 901 161 193 847 656 25 
0.000 000 007 450 580 596 923 828 125 
0.000 000 003 725 290 298 461 914 062 5 
0.000 000 001 862 645 149 230 957 031 25 
0.000 000 000 931 322 574 615 478 515 625 
0.000 000 000 465 661 287 307 739 257 812 5 
0.000 000 000 232 830 643 653 869 628 906 25 
0.000 000 000 116 415 321 826 934 814 453 125 
0.000 000 000 058 207 660 913 467 407 226 562 5 
0.000 000 000 029 103 830 456 733 703 613 281 25 
0.000 000 (>00 014 551 915 228 366 851 806 640 625 
0.000 000 000 007 275 957 614 183 425 903 320 312 5 
0.000 000 000 003 637 978 807 091 712 951 660 156 25 
0.000 000 000 001 818 989 403 545 856 475 830 078 125 
0.000 000 000 000 909 494 701 772 928 237 915 039 062 5 
0.000 000 000 000 454 747 350 886 464 118 957 519 531 25 
0.000 000 000 000 227 373 675 443 232 059 478 759 765 625 
0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5 
0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 25 
0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125 
0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5 
0.000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25 
0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625 
0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5 
0.000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25 
0.000 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328 125 
0.000 000 000 000 000 222 044 604 925 031 308 084 726 333 618 164 062 5 
0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 809 082 031 25 
0.000 000 000 000 000 055 511 151 231 257 827 021 181 583 404 541 015 625 
0.000 000*000 000 000 027 755 575 615 628 913 510 590 791 702 270 507 812 5 
0.000 000 000 000 000 013 877 787 807 814 456 755 295 395 851 135 253 906 25 
0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 925 567 626 953 125 
0.000 000 000 000 000 003 469 446 951 953 614 188 823 848 962 783 813 476 562 5 
0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 391 906 738 281 25 
0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 695 953 369 140 625 . 
0000 000 000 000 000 000 433 680 868 994 201 773 602 981 120 347 976 684 570 312 5 
0.000 000 000 000 000 000 216 840 434 497 100 886 801 490 560 173 988 342 2R5 156 25 
0.000 000 000 000 000 000 108 420 217 248 550 443 400 745 280 086 994 171 142 578 125 
0.000 000 000 000 000 000 054 210 108 624 275 221 700 372 640 043 497 085 571 289 062 5 
0.000 000 000 000 000 000 027 105 054 312 137 610 850 186 320 021 748 542 785 644 531 25 
0.000 000 000 000 000 000 013 552 527 156 068 805 425 093 160 010 874 271 392 822 265 625 
0.000 000 000 000 000 000 006 776 263 578 034 402 712 546 580 005 437 135 696 411 132 812 5 
0.000 000 000 000 000 000 003 388 131 789 017 201 356 273 290 002 718 567 848 205 566 406 25' 
0.000 000 000 000 000 000 001 694 065 894 508 600 678 136 645 001 359 283 924 102 783 203 125 
0.000 000 000 000 000 000 000 847 032 947 254 300 339 068 322 500 679 641 962 051 391 601 562 5 
0.000 000 000 000 000 000 000 423 516 473 627 150 169 534 161 250 339 820 981 025 695 800 781 25 
4 722 366 482 869 645 213 696 72 0.000 000 000 000 000 000 000 211 758 236 813 575 084 767 080 625 169 910 490 512 847 900 390 625 









1 











2 


1 








4 


2 








8 


3 








16 


4 








32 


5 








64 


6 








128 


7 








256 


8 








512 


9 








1 024 


10 








2 048 


11 








4 096 


12 








8 192 


13 








16 384 


14 








32 768 


15 








65 536 


16 








131 072 


17 








262 144 


18 








524 288 


19 








1 048 576 


20 








2 097 152 


21 








4 194 304 


22 








8 388 608 


23 








16 777 216 


24 








33 554 432 


25 








67 108 864 


26 








134 217 728 


27 








268 435 456 


28 








536 870 912 


29 








1 073 741 824 


30 








2 147 483 648 


31 








4 294 967 296 


32 








8 589 934 592 


33 








17 179 869 184 


34 








34 359 738 368 


35 








68 719 476 736 


36 








137 438 953 472 


37 








274 877 906 944 


38 








549 755 813 888 


39 






1 


099 511 627 776 


40 






2 


199 023 255 552 


41 






4 


398 046 511 104 


42 






8 


796 093 022 208 


43 






17 


592 186 044 416 


44 






35 


184 372 088 832 


45 






70 


368 744 177 664 


46 






140 


737 488 355 328 


47 






281 


474 976 710 656 


48 






562 


949 953 421 312 


49 




1 


125 


899 906 842 624 


50 




2 


251 


799 813 685 248 


51 




4 


503 


599 627 370 496 


52 




9 


007 


199 254 740 992 


53 




18 


014 


398 509 481 984 


54 




36 


028 


797 018 963 968 


55 




72 


057 


594 037 927 936 


56 




144 


115 


188 075 855 872 


57 




288 


230 


376 151 711 744 


58 




576 


460 


752 303 423 488 


59 


1 


152 


921 


504 606 846 976 


60 


2 


305 


843 


009 213 693 952 


61 


4 


611 


686 


018 427 387 904 


62 


. 9 


223 


372 


036 854 775 808 


63 


18 


446 


744 


073 709 551 616 


64 


36 


893 


488 


147 419 103 232 


65 


73 


786 


976 


294 838 206 464 


66 


147 


573 


952 


589 676 412 928 


67 


295 


147 


905 


179 352 825 856 


68 


590 


295 


810 


358 705 651 712 


69 


1 180 


591 


620 


717 411 303 424 


70 


2 361 


183 


241 


434 822 606 848 


71 



175 



APPENDIX D 
ALGORITHMS 



All arithmetic operations on full and half words are performed in the 36-bit 
parallel adder. There are two sets of summand inputs to the adder, each set 
of 36 supplying one input to each adder stage. One set supplies the contents 
of AR, its complement, or zero; the other set supplies the contents of BR, its 
complement, or zero. Each stage also has a carry input, which is generated 
by the next less significant stage. Every stage has two outputs; the carry 
already mentioned, and a sum. The 36 sum outputs together form the sum 
of the two input words. The least significant stage has a carry input from the 
logic for performing twos complement arithmetic and incrementing by one. 
The negative of a number is formed at the sum outputs simply by supplying 
the complement of the number at one set of inputs and asserting the carry 
into stage 35. Adder stage 17 has extra input gating so that 1 can be added 
to or subtracted from both halves of AR simultaneously. 

The adder produces a sum in the same way that one adds binary numbers 
using pencil and paper. Each adder stage has three inputs, two summand bits 
and a carry, and two outputs, sum and carry. The sum output of a given 
stage is 1 if any one or all three of the inputs are 1 . The carry out is 1 if two 
or three of the inputs are 1 . Calculations are performed as though the words 
represented 36-bit unsigned numbers, ie the signs are treated just like magni- 
tude bits. In the absence of a carry into the sign stage, adding two numbers 
with the same sign produces a plus sign in the result. The presence of a carry 
gives a positive answer when the summands have different signs. The result 
has a minus sign when there is a carry into the sign bit and the summands 
have the same sign, or the summands have different signs and there is no 
carry. 

Thus the program can interpret the numbers processed in fixed point 
arithmetic as signed numbers with 35 magnitude bits or as unsigned 36-bit 
numbers. A computation on signed numbers produces a result whioh is 
correct as an unsigned 36-bit number even if overflow occurs, but the hard- 
ware interprets the result as a signed number to detect overflow. Adding 
two positive numbers whose sum is greater than or equal to 2^^ gives a nega- 
tive result, indicating overflow; but that result, which has a 1 in the sign bit, 
is the correct answer interpreted as a 36-bit unsigned number in positive 
form. Similarly adding two negatives gives a result which is always correct 
as an unsigned number in negative form. 

All operations discussed below have two operands, one of which is 
supplied to the adder from BR, which acts simply as a buffer and has no 
special input gating. MQ has shift gating so it can function as a low order 
extension of AR for handling double length operands. All actual computa- 
tions take place in the single 36-bit adder, but the sum output can be placed 
in either AR or MQ, and all transfers to MQ from AR or BR are made 
through the adder. In multiplication MQ holds the multiplier and thus 

Dl 



176 

D2 ALGORITHMS 



controls the summation of partial products; as the multiplier is shifted out, 
the low order word of the product is shifted in. In division MQ suppHes the 
low order part of the dividend to AR as the quotient is being constructed in 
MQ. 

In any extended arithmetic operation, the requisite number of steps is 
counted in the 9-bit shift counter SC, which has a carry network for this 
purpose. SC also has a 9-bit adder fomise in computations on floating point 
exponents and size and position calculations in byte manipulation. 



FIXED POINT ALGORITHMS 

Fixed point numbers are explained in detail in §1.1. For convenience let us 
take the computer representation of the positive number x as +[x] where 
the brackets enclose the number in bits 1-35. Similarly the representation 
of -X is -[2^^ -xl or -[1 -xl depending on whether we are regarding num- 
bers as integers or as proper fractions. The most negative number, -2^^, has 
the form -[0] , which is equivalent to the unsigned integer 2^^. 

Addition. There are four cases of addition of two positive 35-bit numbers 
xandy. 

L x+y 

II. i-x) + {-y) 

III. x + (-7), x>y 

IV. x + (-j), x<y 

The operands are held in AR and BR, but it makes no difference which one 
is in which register. The result appears in AR. For convenience in the 
exposition we shall regard the numbers as proper fractions; to view them as 
integers, simply substitute "2^^" for each occurrence of "1". Since the twos 
complement format allows a representation for - 1 , either x or >^ may be 1 in 
II, and y may be 1 in IV. 

I. If X +>' < 1 the adder output placed in AR is +[jc +y] . lfx+y>\ 
the carry out of stage 1 changes the sign. Consequently if the addition of 
two positive numbers gives a negative result, it is apparent that the sum 
exceeds the capacity of the register. The processor detects the overflow by 
checking the sign carries: there is a carry into the sign stage but none out of 
it. AR then contains 

-[;c+>^-l] 

II. Ignoring the carry into the sign bit in the addition of two negatives 
would give 

-[l-x]. 
-U-y] 



+ [l + l-jc->'] 
If X + >- < 1 the carry changes the sign and the result is 



177 

FIXED POINT D3 



[\-x-yl 



which is the representation of -(x +y). If x + y> \ there is no carry into 
the sign, and its absence in the presence of a carry out indicates overflow. 
AR contains 

-^[l-ix+y-D] 

III. Ignoring the carry into the sign in an addition where the signs are 
different would give 

+ M 
-[\~y] 



, -[l+x->^l 

Since x>y, it follows that 1 +x ~y> 1. Hence the carry changes the sign 
and the result is 

+ [x-y] 

When the operand signs are different, the magnitude of the result cannot 
exceed the larger operand magnitude and there can be no overflow. Since 
in this case the positive number is at least as large in magnitude as the 
negative, there is always a carry into the sign, and this added to the operand 
minus sign produces a carry out. 

IV. The addition of numbers of differing signs where the negative has the 
larger magnitude gives 

+ [x]' 
-[\~y] 



[l+x-y] 



Since x <y, then I +x ~y <\. Hence there are no carries associated with 
the sign and no overflow. The above result is the twos complement represen- 
tation of X - y, ie —(y-x). 

Subtraction. The minuend from AC is in AR, and the subtrahend, which 
is either Q,E or the word from location E, is in BR. Subtraction is done 
directly by adding the twos complement of BR to AR. The logic supplies 
the complement of BR to the adder and a carry into the adder LSB. 

Let X be the absolute value of the number in AR, and y the absolute value 
of the number in BR. There are four cases. 



I. 


X - {-y^ 






II. 


i-x^-y 






III. 


x-y, x>y\ 


i~x)-{~y\ 


X <>^ 


IV. 


x-y, x<y\ 


{~x)~i-y\ 


X ^y 



These correspond respectively to the four cases of addition discussed 
previously. 

Multiplication. The multiplier, 0,£ or the contents of location £, is in 
MQ, and the multiphcand from AC is in BR. AR is clear. The 36-step 
procedure is as follows. 



178 

D4 ALGORITHMS 



If MQ35 (the multiplier LSB) is 1 , subtract BR algebraically from AR, but 
put the result in AR shifted one place to the right, with the LSB of the result 
going into MQO, and shift MQ right so a bit of the multiplier is dropped from 
MQ35. Put the sign of the result in ARO and ARl (as though the shift 
followed the subtraction and did not affect the sign but did move it to 
ARl). If MQ35 is 0, simply shift AR and MQ right one, with AR35 going 
into MQO. 

In each subsequent step perform only the shift if the bits moved in and 
out of MQ35 on the previous step were the same. If they were different, add 
or subtract along with the shift: if the shift moved a in and a 1 out, add 
BR to AR; if a 1 in and a out, subtract BR from AR. 

Thus the low order bits of the running sum of partial products are shifted 
into MQ as the multiplier is shifted out. At each step the effect of the multi- 
plicand in BR on the partial sum in AR is one binary order of magnitude 
greater than in the preceding step because the partial sum was shifted right. 
Therefore BR can be combined directly with AR. If MQ35 is initially 0, 
there is no subtraction until a 1 is shifted into it. Simple shifting then 
continues until the next transition (from 1 to 0), following which BR is 
added. 

The process continues in this way, subtracting at every 0-1 transition, 
adding at every 1-0 transition. After 35 steps MQ0~34 contains the low 
half of the product magnitude, and MQ35 contains the sign of the multiplier. 
At the final step, add or subtract as required but put the result directly into 
AR; shift only MQ to move the low magnitude into the correct position and 
make MQO equal to the sign of the whole product. 

If the original operands were both negative and the result is also negative, 
set Overflow; this can occur only when -2^^ is squared. In IMUL, if the high 
word is not null (ie if AR is neither clear nor all Is), set Overflow; move MQ 
to AR for storage of the low word. 

To see that this procedure results in a correct product, consider the posi- 
tive binary integer 

100111011 

876543210 

where the decimal digits below the binary digits are the powers of 2 corres- 
ponding to the bit positions. This number is obviously equal to 

1 00000000 
+ 111 000 
+ 1 1 

Now an n-mi strmg ^f Is whose rightmost bit corresponds to 2*^15 equal to 
2k+n _ 2^^ or equivafently 2^(2" - 2°), ie 2" - 2*^ is a string of « Is and the 2* 
shifts the string left')?: places. Hence 

100000000 = 2^^i-2« = 2^-2« 

111000 - 2^^3-2^ = 2^-2^ 

1 1 =z 22^^-2^ = 2^-2^ 



100111011 = 2^-2^ + 2^-2^ + 22-2'^ 

In this last representation, each power of 2 that is subtracted corresponds to 



179 

FIXED POINT D5 



a transition from to 1 (scanning right to left), whereas each that is added 
corresponds to a 1-0 transition. The largest term corresponds to the transi- 
tion to the sign bit, which is for a positive number. The multiplication 
algorithm interprets the multiplier in this manner, alternately subtracting 
and adding the multiplicand to the partial sum in the order-of-magnitude 
positions corresponding to the transitions. If a multiplier of the same magni- 
tude were negative, it would have the form 

10 11 000 1 1 

-876543210 

in which the extra bit at the left represents the sign. The number is now 
equivalent to 

-2^+2^-2^ + 23-2^ + 2^-2° 

wherein opposite signs correspond to opposite transitions. The algorithm 
may thus use exactly the same sequence for a negative multiplier: this time 
the subtraction of greatest magnitude is detected by the transition to the 
sign bit, which is now 1 . 

Division. The divisor, 0,£ or the contents of location E, is in BR. In 
DIV the high and low halves of the dividend from two accumulators are in 
AR and MQ respectively. In IDIV the one-word dividend from AC is in AR. 
The two types of division differ mainly in setting up the dividend; in both 
cases the algorithm processes a positive dividend to get a positive quotient. 

In DIV if the dividend is negative (ARO = 1), make it positive and set the 
negative dividend flag. To negate the dividend, move the low word to AR 
and the complement of the high word to MQ. Then move the negative of 
the low word back to MQ and the complement of the high word back to AR. 
Now the double length negative of the original dividend is in AR and MQ 
unless MQ is clear; in this event add 1 to AR to give the twos complement 
negative of the high word. Once the dividend is in positive form shift MQ 
left one place to close the hole between the two halves; in other words drop 
the low sign and get the 70-bit magnitude into ARl -35, MQO-34. 

If the IDIV dividend in AR is negative, negate it and set the negative 
dividend flag. Move the one word dividend in positive form to MQ and clear 
AR. Shift MQ left, as the algorithm operates on a double length dividend in 
both types of division although the high part is null in this case. 

After the dividend is set up, compare the divisor with it to determine 
whether the division can be performed. Subtract the absolute value of the 
divisor from the high half of the dividend (if the divisor is positive, subtract 
it; if negative, add it). Since the dividend is positive, the result is also 
positive if the magnitude of the divisor is less than or equal to the number in 
AR. For a fixed fraction, the divisor is subtracted from the actual dividend 
and no overflow is allowed. For a fixed integer, AR is clear and the result is 
positive only for a zero divisor; the worst possible case is the division of 
235-1 by 1, whose integral result can be accommodated. (Placing the one 
word dividend in MQ effectively multipHes it by 2~^^ making it the frac- 
tional part of a two word dividend with the binary point in the middle. The 
quotient is then a proper fraction, which is multiplied by 2^^ simply by ' 
interpreting it as an integer.) Thus if the result of this initial subtraction is 



180 

ALGORITHMS 

positive, set Overflow and No Divide, and terminate the procedure so the 
processor goes on to the next instruction. Dividing by zero is of course 
meaningless. The reason for prohibiting a fractional division where the result 
would be greater than 1 is that it is impossible to determine the position of 
the binary point in the quotient. So it is up to the programmer to shift the 
dividend to the correct position beforehand. If the result of the initial sub- 
traction is negative, the division can be performed and the processor goes 
into the division loop. 

In division on paper, one subtracts out the divisor the number of times it 
goes into the dividend, then shifts the dividend one place to the left (or the 
divisor to the right) and again subtracts out. In binary computations the 
divisor goes into the dividend either once or not at all. Each subtraction of 
the divisor thus generates a single bit of the quotient. If the subtraction 
leaves a positive difference, le if the dividend is larger than the divisor, a 1 is 
entered into the quotient. If the difference is negative, a is entered. To 
compensate for subtracting too much, the hardware could add the divisor 
back into the dividend before going to the next subtraction step. But the 
PDP-10 algorithm instead shifts first and adds the divisor back in at the new 
position. It then continues to shift and add putting Os into the quotient 
until the result again becomes positive. This procedure generates the same 
quotient without ever going back a step. 

The hardware procedure is as follows. As each addition or subtraction is 
formed in the adder, put the result in AR shifted one place to the left with 
AR35 receiving a new bit of the dividend from MQO, and shift MQ left 
bringing in a bit of the quotient at MQ35. The bit brought in is the comple- 
ment of the sign from the adder: if the divisor does not go into the dividend, 
the resulting minus sign (1) produces a quotient bit; if the divisor does go 
in, the plus sign gives a 1 . Each step loads one bit of the quotient into MQ35, 
and the low half of the dividend is shifted out of MQ as the quotient is 
shifted in. 

The first step is the test subtraction. In each subsequent step, subtract 
the absolute value of the divisor if the quotient bit generated in the previous 
step is 1, but add it back in if the quotient bit is 0. Since the divisor may 
have either sign, subtract it algebraically if its sign differs from the quotient 
bit, add it if its sign is the same. 

The hardware executes 36 steps to generate 35 magnitude bits. The initial 
test step must give a 0, which serves as the sign since we are producing a 
positive quotient. In the final step put the result of the addition or subtrac- 
tion directly in AR without shifting so the remainder is in the correct 
position, but shift MQ left putting the sign from the first step in MQO and 
bringing in the last quotient bit. (The bit dropped out of MQO is superfluous; 
it was brought into MQ3| when the hole was closed between the dividend 
halves.) ' 

To complete the division we must make sure the remainder is correct and 
determine the correct signs of the results. Since the operations were per- 
formed on positive operands, the remainder should also be positive. A 
negative remainder indicates that too much has been subtracted. To correct 
this add the absolute value of the divisor back in. If the negative dividend 
flag is set, negate AR so the remainder has the sign of the original dividend. 



181 

FLOATING POINT D7 



Now move the corrected remainder to MQ and move the quotient to AR. 
If the negative dividend flag and the divisor sign are of opposite states, 
negate AR to produce the correct quotient sign. The correct quotient and 
remainder are now in AR and MQ ready for storage. 

As an example of the way this algorithm operates, consider a division of 
3-bit fixed fractions with a dividend of +.100100 and a divisor of +.101. 
By paper computation we obtain the quotient this way. 

.111 
101 



1 100.100 
10 1 


10 00 
1 01 


no 

101 



Taking the processor registers to be four bits in length, AR contains 0.100, 
MQ has 0. 100, and BR has 0. 101 . Before starting we close the hole changing 
MQ to 1 .000. The sequence has four steps. 

0.100 1.000 " 
- 0.101 
1.111 

1 ^ 1.111 0.000 

+ 0.101 
0.100 

2 ^ 1.000 0.001 

- 0.101 
0.011 

3 ^ 0.110 0.011 

- 0.101 
0.001 

4 0.001 ^0.111 

The quotient is in MQ at the right, the remainder in AR at the left. 



FLOATING POINT ALGORITHMS 

§1.1 explains floating point numbers and §2.6 discusses the general charac- 
teristics of floating point arithmetic. Exponent computations are done in 
the SC adder using the exponents and signs from the floating point operands. 
Remember, the sign is that of the whole number, not of the exponent. 
Although bits 1-8 of a floating point number represent an exponent in the 
range -128 to +127, the discussion is entirely in terms of the excess 128 
exponents in positive foTm,ie the set of numbers 0-255. Computations 
generally use twos complement operations even though the exponent in a 



182 



ALGORITHMS 



negative number is a ones complement. The SC sign bit is used to detect 
exponent overflow and underflow. 

After exponent calculations are complete, operations on the fractions are 
done by the fixed point logic in AR, BR and MQ. Bits 1 -8 of AR and BR 
are filled with null bits, Os in a positive number, Is in a negative. Double 
length operands are in AR and MQ with MQ8-35 forming a magnitude 
extension of AR. In almost all circumstances the logic treats ARO-35 and 
MQ8-35 as a single 64-bit register; in all two-word shifting AR35 is con- 
nected to MQ8 and MQO-7 is ignored. Except in division the fixed point 
calculation generates a double length fraction, which is shifted arithmetically 
(in right shifting the sign goes into ARl ; in left shifting the sign is unaffected 
and Os enter MQ35). Almost all floating point instructions normalize the 
result, thus making use of the low order part even though the instruction 
may store only the high order word. 

Addition, Subtraction. E,0 or the word from location E is in BR, and AC 
is in AR. For subtraction move the negative of the subtrahend from BR to 
AR and move the minuend from AR to BR. This reduces subtraction to 
addition, so the rest of the algorithm is the same for both. 

The initial objective is to determine the difference between the exponents 
and to determine which exponent is the larger. If the signs of the operands 
differ, add the exponents into SC. If the signs are the same, subtract the BR 
exponent from the AR exponent by adding the twos complement. Let x 
and y be the AR and BR exponents in positive form. The table below shows 
the calculations as a function of the operand signs, and the sign of the result 
in SC as a function both of the operand signs and the relative values of x 
and y. 



AR+, BR+ 


AR+, BR- 


AR- 


BR+ 


AR-, BR- 


+[x] 


Hx] 


-[255- 


-X] 


-[255 -X] 


-[256 -y] 


-[255 -y] 


Hy] 




+ [l+y] 


-[256 + x->'] 


-[255-^x-y] 


-[255- 


-x-\-y] 


-[256~;c+>'] 


SC+ sc- 


SC+ sc- 


SC+ 


sc- 


SC+ SC- 


X >y X <y 


X >y X <y 


x<y 


x>y 


x<y x>y 



As can be seen from the above, if AR already contains the number with the 
smaller exponent, the SC and AR signs differ. Hence if the SC and AR signs 
are the same, switch BR and AR so the number with the smaller exponent 
can be shifted. If the exponents are equal, the signs may or may not be the 
same but it matters not whether the transfer takes place. 

To control the shifting we must now get the negative of the difference 
between the exponents. Let d he Ix -y\. There are four cases as a function 
of the SC sign and whether the AR and BR signs are equal. The second 
column lists the present contents of SC, the third tells what must be done to 
arrive at -[256 -fi] in SC. 

SC+,ARO = BRO +[d] Negate SC 

SC+, ARO ¥= BRO +[d-l] Complement SC 



183 

FLOATING POINT D9 



SC-,ARO-BRO -[256 -rf] Do nothing 

SC-, ARO =r^ BRO -[255-6?] Add 1 to SC 

If (i < 64 (indicated by a negative SC with a in either SCI or SC2) nullify 
ARl-8 and shift AR and MQ right d places so its bits correctly match the 
BR bits in order of magnitude. If £^ > 64 clear AR for its contents are of 
no significance. 

Now move the larger exponent from BR to SC in positive form, nullify 
BRl-8, and add BR and AR into AR as fixed fractions. Finally enter the 
normalizing sequence. 

This sequence first tests for a zero result. If AR and MQ8-35 are clear, 
bypass the rest of the procedure. If the fractional result has overflowed into 
AR8 (indicated by ARO i- AR8 or AR8 = 1 and AR9-35 = 0), shift right 
and increase the exponent by one. The number is now normalized. 

Complement the exponent in SC. If the instruction is not UFA and the 
number is not normalized go into the normalizing loop. In each step shift 
the double length fraction left and add 1 to the negative exponent 
(decreasing its magnitude by 1 ). Terminate the loop when the fraction is 
normahzed, indicated by the sign and the MSB of the fraction being different 
(ARO ^ AR9) or the magnitude being Va (AR9 = 1 and ARlO-35 - 0). 

If the instruction specifies rounding, adjust the high fraction so it is 
rounded and is in twos complement form if negative. The rounding is away 
from zero. For a positive result the high fraction must be increased if the 
low fraction is greater than half the value of the high fraction LSB. In a 
negative result the high fraction is a ones complement, which is one greater 
in magnitude than the twos complement. Hence it is already rounded and 
should be decreased in magnitude if the low fraction is < ViLSB. In either 
case add 2"^'' into AR if MQ8 is 1 unless MQ9-35 is clear in a negative 
number. A 1 in MQ8 indicates a low fraction > VzLSB in a positive number, 
< y2LSB in a negative number. The condition that MQ9-35 not be zero in 
a negative number is the case where the low fraction is exactly ^/zLSB. If the 
high fraction is actually changed, renormalize it. A single normalizing shift 
is all that is required and it occurs in only two cases: a right shift when 
1-2"^'' is rounded, a left shift when -Vi is changed to a correct twos 
complement. 

Once the number has been normalized (and rounded if necessary) the 
exponent is in negative form. Thus if the SC sign bit is 0, set Overflow and 
Floating Overflow. If SCI is also 0, the sign bit must have been changed by 
decreasing the exponent, so also set Floating Underflow (the maximum 
possible exponent overflow is 128 giving an SC contents of 111^, and this 
can occur only in division). Insert the exponent in correct form into ARl -8. 

The result is now ready to store from AR unless the instruction is in long 
mode. To ready the double length result subtract 27 from the positive expo- 
nent in SC. Save the high word in MQ, and move the low word to AR, but 
only if the decreased exponent is still positive. If the sign is 1 , the true 
exponent of the low word is less than -128, so clear AR. (Note that this 
condition is also true if the low exponent is > 127, which can occur only if 
the high exponent is > 154.) If the low word is nonzero, shift AR right 
one place to put the fraction in bits 9-35 (remember that all shift operations 



184 

DIO ALGORITHMS 



use MQ8-35), clear ARO so the low word has a positive sign even if the 
double length fraction is negative, and insert the low exponent in positive 
form in bits 1 -8. Finally switch AR and MQ so the high and low words are 
in correct position for storage. 

Scaling. The 9-bit signed scale factor from bits 18 and 28-35 of E is in 
SC, and AC is in AR and BR. If the floating point number being scaled is 
positive, simply add the sign and exponent from BRO-8 to SC; if the number 
is negative, add the complement of BRO-8 to SC. Let x be the exponent in 
positive form and let y be the absolute value of the scale factor. There are 
only two cases, 

+ [x] Hx] 

Hy] -[256-y] 

Hx-^y] Hx-y] 

and in either the result is in positive form in SC. 

Now enter the normalizing sequence described under floating addition. 
Only left shifting can occur bringing Os in from MQ. The result can be zero, 
and exponent overflow or underflow can occur; but there is no rounding, 
and at the end the one-word result is in AR ready for storage. 

Multiplication. £",0 or the word from location E is in BR, and AC is in 
AR. Place the AR exponent in positive form in SC, and add the positive 
form of the BR exponent to it. Since both are in excess- 1 28 code, subtract 
128. Save the result in the floating exponent register FE so SC can be used 
to control the multiphcation of the fractions. 

Nullify the exponent parts of AR and BR. Move the multiplier from BR 
to MQ and the multiplicand from AR to BR. Clear AR. Now multiply the 
fractions by the same procedure given for fixed point multiplication with 
the following differences: 

♦ There are only 28 steps instead of 36. 

♦ The shift register extension of AR for the construction of the product is 
MQ8-35. As the multiplier is shifted out, bits of the product come in 
at MQ8. 

♦ In the final step place the adder output directly into AR but do not shift 
MQ - the low fraction is in MQ8-34, the correct position for normalization. 

Clear MQ35, move the exponent back to SC, and enter the normalizing 
sequence described under floating addition. If the operands are normalized, 
at most one left shift is needed to normalize the result. 

Division. The divisor, E^O or the contents of location E, is in BR. The 
dividend from AC is in AR. In long mode the low half of the dividend from 
the second accumulator is in MQ; otherwise MQ is clear. 

If the dividend is negative, make it positive and set the negative dividend 
flag. Except in long mode, negate the dividen(i simply by negating AR. For 
long mode follow the procedure given for DIV in the second paragraph of 
the fixed division algorithm. With a floating point operand the left MQ shift 
puts the low fraction in MQ8-34. 

Place the AR exponent in positive form in SC. Subtract the magnitude of 
the BR exponent from it by adding the negative form of the exponent (ones 
complement) plus 1. Since the excess-128 factors cancel in the subtraction, 
add 128. Save the result in the floating exponent register FE so SC can be 



185 

FLOATINGPOINT Dll 



used to control the division of the fractions. 

Nuihfy the exponent parts of AR and BR. Subtract the absolute value of 
the divisor from the high half of the dividend. If the result is positive, 
indicating the divisor is less than or equal to the dividend, shift AR and MQ 
right and increase the exponent in SC by 1 . Save the adjusted exponent in 
FE. The shift divides by 2, so if the operands are normalized, the dividend 
must now be less than the divisor. 

Now divide the fractions by the same procedure given for fixed point 
fractional division with the following differences; 

♦ Since the dividend has already been adjusted, the test in the first step 
stops the division only if the divisor is zero, or is unnormalized and less than 
the dividend. A normalized divisor cannot cause vthe quotient to overflow. 
If the result of the initial subtraction is positive, terminate the procedure 
and set Floating Overflow as well as Overflow and No Divide. 

♦ Instead of 36 steps there are only 29 if the instruction specifies rounding, 
otherwise 28. 

♦ The shift register extension of AR is MQ8~35. As quotient bits are 
brought in at MQ35, dividend bits are suppHed to AR35 from MQ8. The 
shifting clears MQO-7. 

♦ The MQ shift in the final step places a 27-bit quotient fraction in MQ9-35 
or a 28-bit fraction in MQ8-35. 

♦ As in the fixed point algorithm generate the correct signed remainder, put 
it in MQ, and move the quotient to AR but leave it positive. 

If the instruction specifies rounding, shift AR right placing the 27-bit 
fraction in the correct position, and if the bit shifted out of AR35 is 1, add 
it back into AR35 to round the positive quotient. If the quotient is zero 
bypass the rest of the procedure. The reaminder will also be zero except in 
an FDVL where the double length dividend is unnormalized and its high 
fraction is zero. 

Complement the exponent in SC. If the instruction uses normahzed 
operands the initial dividend adjustment guarantees that the quotient will be 
normahzed. If it is not, shift AR left (bringing Os into AR35) until a 1 
appears in AR9, each time increasing the negative exponent by 1 (decreasing 
its magnitude). 

Since the exponent is in negative form, if SCO is 0, set Overflow and 
Floating Overflow. If SCI is also 0, the sign bit must have been changed by 
decreasing the exponent, so also set Floating Underflow. Insert the exponent 
in correct form into ARl-8. If the negative dividend flag and the divisor 
sign (BRO) are of opposite states, negate AR to produce the correct quotient 
sign. 

The quotient is now ready for storage from AR and the remaining opera- 
tions are performed only for long mode. Save the quotient in BR and bring 
the high half of the original dividend from AC to AR. Put the dividend 
exponent in SC. Decrease its magnitude by 26 if the dividend was shifted 
right at the beginning to allow the division to be performed; otherwise 
decrease it by 27. Move the remainder to AR and insert the exponent in it 
provided the remainder is not zero and the exponent is within the proper 
range, -128 to 127 (the test is that the sign resulting from the exponent 
calculation is the same as the sign of the remainder). If the exponent is 



186 

D12 ALGORITHMS 



outside that range clear AR; the assumption is that the remainder is of no 
significance (ie the exponent is too small). Move the remainder with its 
correct exponent from AR to MQ and put the quotient back in AR. The 
two words are now ready for storage. 

Double Precision Division. The software routine that performs double 
precision floating point division and the algorithm it utilizes are given at 
the end of §2.1 1 . FDVL performs the division 

A/b = q + rl-^'Vb 

where q and r are the quotient and remainder. In a double precision 
division the divisor is of the form 

B = b + c/2-2'^ 

Using the expansion 






x+y X 

and letting x — b and y — dl''^'^ gives 



b^ b^ 



Multiplying out and gathering like terms gives 

- = q+~(r-qd)2-^'-~{r-qd)2-'^ + ^Ar-qd)2-''- .... 
B b b^ b^ 

where the first two terms on the right are those in the equation at the 
bottom of page 2-67. 

The ratio of adjacent terms is 

T„ b 

In an alternating convergent series, the error due to truncation is smaller 
than the first term dropped. Therefore 

^2-2^ 
\Error\ < r„ 



Since the maximum value of d is less than 1 and the minimum value of b 
(normahzed) is Vz, 

lErrorl < T„2-^^